llvm::RISCVSubtarget Class Reference

#include "Target/RISCV/RISCVSubtarget.h"

Inheritance diagram for llvm::RISCVSubtarget:

Public Types
enum	RISCVProcFamilyEnum : uint8_t { Others , SiFive7 , MIPSP8700 , Andes45 }
enum	RISCVVRGatherCostModelEnum : uint8_t { Quadratic , NLog2N }

Public Member Functions
	RISCVSubtarget (const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)
	~RISCVSubtarget () override
void	ParseSubtargetFeatures (StringRef CPU, StringRef TuneCPU, StringRef FS)
const RISCVFrameLowering *	getFrameLowering () const override
const RISCVOptions &	getCLOpts () const
const RISCVInstrInfo *	getInstrInfo () const override
const RISCVRegisterInfo *	getRegisterInfo () const override
const RISCVTargetLowering *	getTargetLowering () const override
void	mirFileLoaded (MachineFunction &MF) const override
bool	enableMachineScheduler () const override
bool	enablePostRAScheduler () const override
Align	getPrefFunctionAlignment () const
Align	getPrefLoopAlignment () const
RISCVProcFamilyEnum	getProcFamily () const
	Returns RISC-V processor family.
RISCVVRGatherCostModelEnum	getVRGatherCostModel () const
bool	hasYInstructions () const
bool	hasStdExtZvl () const
bool	hasStdExtFOrZfinx () const
bool	hasStdExtDOrZdinx () const
bool	hasStdExtZfhOrZhinx () const
bool	hasStdExtZfhminOrZhinxmin () const
bool	hasHalfFPLoadStoreMove () const
bool	hasCLZLike () const
bool	hasCTZLike () const
bool	hasCPOPLike () const
bool	hasREV8Like () const
bool	hasREVLike () const
bool	hasBEXTILike () const
bool	hasConditionalMoveFusion () const
bool	hasShlAdd (int64_t ShAmt) const
bool	is64Bit () const
bool	isLittleEndian () const
MVT	getXLenVT () const
unsigned	getXLen () const
bool	useMIPSLoadStorePairs () const
bool	useMIPSCCMovInsn () const
unsigned	getFLen () const
Align	getZilsdAlign () const
unsigned	getELen () const
unsigned	getRealMinVLen () const
unsigned	getRealMaxVLen () const
std::optional< unsigned >	getRealVLen () const
template<typename Quantity>
Quantity	expandVScale (Quantity X) const
	If the ElementCount or TypeSize X is scalable and VScale (VLEN) is exactly known, returns X converted to a fixed quantity.
RISCVABI::ABI	getTargetABI () const
bool	isSoftFPABI () const
const std::bitset< 32 > &	getUserReservedXRegs () const
	Returns the X registers reserved by the reserve-xN features, indexed by N.
bool	isRegisterReservedByUser (Register i) const override
TargetRegisterClass const *	getLargestFPRegClass () const
bool	isXRaySupported () const override
bool	hasVInstructions () const
bool	hasVInstructionsI64 () const
bool	hasVInstructionsF16Minimal () const
bool	hasVInstructionsF16 () const
bool	hasVInstructionsBF16Minimal () const
bool	hasVInstructionsF32 () const
bool	hasVInstructionsF64 () const
bool	hasVInstructionsBF16 () const
bool	hasVInstructionsAnyF () const
bool	hasVInstructionsFullMultiply () const
unsigned	getMaxInterleaveFactor () const
bool	hasOptimizedSegmentLoadStore (unsigned NF) const
bool	isPExtPackedType (MVT VT) const
bool	isPExtPackedDoubleType (MVT VT) const
unsigned	getDLenFactor () const
const SelectionDAGTargetInfo *	getSelectionDAGInfo () const override
const CallLowering *	getCallLowering () const override
InstructionSelector *	getInstructionSelector () const override
const LegalizerInfo *	getLegalizerInfo () const override
const RISCVRegisterBankInfo *	getRegBankInfo () const override
const InlineAsmLowering *	getInlineAsmLowering () const override
bool	isTargetAndroid () const
bool	isTargetFuchsia () const
bool	useConstantPoolForLargeInts () const
unsigned	getMaxBuildIntsCost () const
unsigned	getMispredictionPenalty () const override
unsigned	getLoadLatency () const override
bool	useRVVForFixedLengthVectors () const
bool	enableSubRegLiveness () const override
bool	enableMachinePipeliner () const override
bool	useDFAforSMS () const override
bool	useAA () const override
	Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
unsigned	getCacheLineSize () const override
unsigned	getPrefetchDistance () const override
unsigned	getMinPrefetchStride (unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override
unsigned	getMaxPrefetchIterationsAhead () const override
bool	enableWritePrefetching () const override
unsigned	getMinimumJumpTableEntries () const
unsigned	getTailDupAggressiveThreshold () const
unsigned	getMaxStoresPerMemset (bool OptSize) const
unsigned	getMaxGluedStoresPerMemcpy () const
unsigned	getMaxStoresPerMemcpy (bool OptSize) const
unsigned	getMaxStoresPerMemmove (bool OptSize) const
unsigned	getMaxLoadsPerMemcmp (bool OptSize) const
uint8_t	getMaxVectorCoalesceElts () const
MISched::Direction	getPostRASchedDirection () const
bool	isJumpExpensive () const
void	overrideSchedPolicy (MachineSchedPolicy &Policy, const SchedRegion &Region) const override
void	overridePostRASchedPolicy (MachineSchedPolicy &Policy, const SchedRegion &Region) const override

Protected Member Functions
unsigned	getMaxRVVVectorSizeInBits () const
unsigned	getMinRVVVectorSizeInBits () const

Protected Attributes
std::unique_ptr< const SelectionDAGTargetInfo >	TSInfo
std::unique_ptr< CallLowering >	CallLoweringInfo
std::unique_ptr< InstructionSelector >	InstSelector
std::unique_ptr< LegalizerInfo >	Legalizer
std::unique_ptr< RISCVRegisterBankInfo >	RegBankInfo
std::unique_ptr< InlineAsmLowering >	InlineAsmLoweringInfo

Detailed Description

Definition at line 93 of file RISCVSubtarget.h.

Member Enumeration Documentation

RISCVProcFamilyEnum

enum llvm::RISCVSubtarget::RISCVProcFamilyEnum : uint8_t

Enumerator
Others
SiFive7
MIPSP8700
Andes45

Definition at line 96 of file RISCVSubtarget.h.

RISCVVRGatherCostModelEnum

enum llvm::RISCVSubtarget::RISCVVRGatherCostModelEnum : uint8_t

Enumerator
Quadratic
NLog2N

Definition at line 102 of file RISCVSubtarget.h.

Constructor & Destructor Documentation

RISCVSubtarget()

RISCVSubtarget::RISCVSubtarget	(	const Triple &	TT,
		StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS,
		StringRef	ABIName,
		unsigned	RVVVectorBitsMin,
		unsigned	RVVVectorLMULMax,
		const TargetMachine &	TM )

Definition at line 99 of file RISCVSubtarget.cpp.

References const, getCLOpts(), isLittleEndian(), and TSInfo.

~RISCVSubtarget()

RISCVSubtarget::~RISCVSubtarget ( )

overridedefault

Member Function Documentation

enableMachinePipeliner()

bool RISCVSubtarget::enableMachinePipeliner ( ) const

override

Definition at line 234 of file RISCVSubtarget.cpp.

enableMachineScheduler()

bool llvm::RISCVSubtarget::enableMachineScheduler ( ) const

inlineoverride

Definition at line 170 of file RISCVSubtarget.h.

enablePostRAScheduler()

bool llvm::RISCVSubtarget::enablePostRAScheduler ( ) const

inlineoverride

Definition at line 172 of file RISCVSubtarget.h.

enableSubRegLiveness()

bool RISCVSubtarget::enableSubRegLiveness ( ) const

override

Definition at line 232 of file RISCVSubtarget.cpp.

enableWritePrefetching()

bool llvm::RISCVSubtarget::enableWritePrefetching ( ) const

inlineoverride

Definition at line 439 of file RISCVSubtarget.h.

expandVScale()

template<typename Quantity>

Quantity llvm::RISCVSubtarget::expandVScale ( Quantity X ) const

inline

If the ElementCount or TypeSize X is scalable and VScale (VLEN) is exactly known, returns X converted to a fixed quantity.

Otherwise returns X unmodified.

Definition at line 290 of file RISCVSubtarget.h.

References getRealVLen(), llvm::RISCV::RVVBitsPerBlock, and X.

getCacheLineSize()

unsigned llvm::RISCVSubtarget::getCacheLineSize ( ) const

inlineoverride

Definition at line 424 of file RISCVSubtarget.h.

getCallLowering()

const CallLowering * RISCVSubtarget::getCallLowering ( ) const

override

Definition at line 127 of file RISCVSubtarget.cpp.

References CallLoweringInfo, and getTargetLowering().

getCLOpts()

const RISCVOptions & llvm::RISCVSubtarget::getCLOpts ( ) const

inline

Definition at line 159 of file RISCVSubtarget.h.

Referenced by llvm::RISCVRegisterInfo::getRegAllocationHints(), isConvertibleToVMV_V_V(), and RISCVSubtarget().

getDLenFactor()

unsigned llvm::RISCVSubtarget::getDLenFactor ( ) const

inline

Definition at line 370 of file RISCVSubtarget.h.

getELen()

unsigned llvm::RISCVSubtarget::getELen ( ) const

inline

Definition at line 267 of file RISCVSubtarget.h.

References assert(), hasVInstructions(), and hasVInstructionsI64().

getFLen()

unsigned llvm::RISCVSubtarget::getFLen ( ) const

inline

Definition at line 247 of file RISCVSubtarget.h.

getFrameLowering()

const RISCVFrameLowering * llvm::RISCVSubtarget::getFrameLowering ( ) const

inlineoverride

Definition at line 156 of file RISCVSubtarget.h.

Referenced by llvm::RISCVMachineFunctionInfo::RISCVMachineFunctionInfo().

getInlineAsmLowering()

const InlineAsmLowering * RISCVSubtarget::getInlineAsmLowering ( ) const

override

Definition at line 120 of file RISCVSubtarget.cpp.

References getTargetLowering(), and InlineAsmLoweringInfo.

getInstrInfo()

const RISCVInstrInfo * llvm::RISCVSubtarget::getInstrInfo ( ) const

inlineoverride

Definition at line 160 of file RISCVSubtarget.h.

Referenced by lowerRISCVVMachineInstrToMCInst(), llvm::RISCVRegisterInfo::lowerSegmentSpillReload(), and runMakeCompressibleOpt().

getInstructionSelector()

InstructionSelector * RISCVSubtarget::getInstructionSelector ( ) const

override

Definition at line 133 of file RISCVSubtarget.cpp.

References llvm::createRISCVInstructionSelector(), getRegBankInfo(), and InstSelector.

getLargestFPRegClass()

TargetRegisterClass const * llvm::RISCVSubtarget::getLargestFPRegClass ( ) const

inline

Definition at line 310 of file RISCVSubtarget.h.

Referenced by getLargestFPRegisterOrZero().

getLegalizerInfo()

const LegalizerInfo * RISCVSubtarget::getLegalizerInfo ( ) const

override

Definition at line 142 of file RISCVSubtarget.cpp.

References Legalizer.

getLoadLatency()

unsigned RISCVSubtarget::getLoadLatency ( ) const

override

Definition at line 194 of file RISCVSubtarget.cpp.

Referenced by getMaxBuildIntsCost().

getMaxBuildIntsCost()

unsigned RISCVSubtarget::getMaxBuildIntsCost

(

)

const

Definition at line 178 of file RISCVSubtarget.cpp.

References getLoadLatency().

getMaxGluedStoresPerMemcpy()

unsigned llvm::RISCVSubtarget::getMaxGluedStoresPerMemcpy ( ) const

inline

Definition at line 452 of file RISCVSubtarget.h.

getMaxInterleaveFactor()

unsigned llvm::RISCVSubtarget::getMaxInterleaveFactor ( ) const

inline

Definition at line 340 of file RISCVSubtarget.h.

References hasVInstructions().

getMaxLoadsPerMemcmp()

unsigned llvm::RISCVSubtarget::getMaxLoadsPerMemcmp ( bool OptSize ) const

inline

Definition at line 466 of file RISCVSubtarget.h.

getMaxPrefetchIterationsAhead()

unsigned llvm::RISCVSubtarget::getMaxPrefetchIterationsAhead ( ) const

inlineoverride

Definition at line 436 of file RISCVSubtarget.h.

getMaxRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits ( ) const

protected

Definition at line 198 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMaxVLen().

getMaxStoresPerMemcpy()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemcpy ( bool OptSize ) const

inline

Definition at line 456 of file RISCVSubtarget.h.

getMaxStoresPerMemmove()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemmove ( bool OptSize ) const

inline

Definition at line 461 of file RISCVSubtarget.h.

getMaxStoresPerMemset()

unsigned llvm::RISCVSubtarget::getMaxStoresPerMemset ( bool OptSize ) const

inline

Definition at line 447 of file RISCVSubtarget.h.

getMaxVectorCoalesceElts()

uint8_t llvm::RISCVSubtarget::getMaxVectorCoalesceElts ( ) const

inline

Definition at line 471 of file RISCVSubtarget.h.

getMinimumJumpTableEntries()

unsigned RISCVSubtarget::getMinimumJumpTableEntries

(

)

const

Definition at line 252 of file RISCVSubtarget.cpp.

getMinPrefetchStride()

unsigned llvm::RISCVSubtarget::getMinPrefetchStride ( unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall ) const

inlineoverride

Definition at line 430 of file RISCVSubtarget.h.

getMinRVVVectorSizeInBits()

unsigned RISCVSubtarget::getMinRVVVectorSizeInBits ( ) const

protected

Definition at line 211 of file RISCVSubtarget.cpp.

References assert(), hasVInstructions(), and llvm::report_fatal_error().

Referenced by getRealMinVLen(), and useRVVForFixedLengthVectors().

getMispredictionPenalty()

unsigned RISCVSubtarget::getMispredictionPenalty ( ) const

override

Definition at line 189 of file RISCVSubtarget.cpp.

getPostRASchedDirection()

MISched::Direction llvm::RISCVSubtarget::getPostRASchedDirection ( ) const

inline

Definition at line 475 of file RISCVSubtarget.h.

Referenced by overridePostRASchedPolicy().

getPrefetchDistance()

unsigned llvm::RISCVSubtarget::getPrefetchDistance ( ) const

inlineoverride

Definition at line 427 of file RISCVSubtarget.h.

getPrefFunctionAlignment()

Align llvm::RISCVSubtarget::getPrefFunctionAlignment ( ) const

inline

Definition at line 174 of file RISCVSubtarget.h.

getPrefLoopAlignment()

Align llvm::RISCVSubtarget::getPrefLoopAlignment ( ) const

inline

Definition at line 177 of file RISCVSubtarget.h.

getProcFamily()

RISCVProcFamilyEnum llvm::RISCVSubtarget::getProcFamily ( ) const

inline

Returns RISC-V processor family.

Avoid this function! CPU specifics should be kept local to this class and preferably modeled with SubtargetFeatures or properties in initializeProperties().

Definition at line 185 of file RISCVSubtarget.h.

getRealMaxVLen()

unsigned llvm::RISCVSubtarget::getRealMaxVLen ( ) const

inline

Definition at line 275 of file RISCVSubtarget.h.

References getMaxRVVVectorSizeInBits().

Referenced by getRealVLen().

getRealMinVLen()

unsigned llvm::RISCVSubtarget::getRealMinVLen ( ) const

inline

Definition at line 271 of file RISCVSubtarget.h.

References getMinRVVVectorSizeInBits().

Referenced by getRealVLen().

getRealVLen()

std::optional< unsigned > llvm::RISCVSubtarget::getRealVLen ( ) const

inline

Definition at line 280 of file RISCVSubtarget.h.

References getRealMaxVLen(), and getRealMinVLen().

Referenced by expandVScale(), and llvm::RISCVRegisterInfo::lowerSegmentSpillReload().

getRegBankInfo()

const RISCVRegisterBankInfo * RISCVSubtarget::getRegBankInfo ( ) const

override

Definition at line 148 of file RISCVSubtarget.cpp.

References RegBankInfo.

Referenced by getInstructionSelector().

getRegisterInfo()

const RISCVRegisterInfo * llvm::RISCVSubtarget::getRegisterInfo ( ) const

inlineoverride

Definition at line 161 of file RISCVSubtarget.h.

Referenced by isConvertibleToVMV_V_V(), isRegisterReservedByUser(), lowerRISCVVMachineInstrToMCInst(), llvm::RISCVRegisterInfo::lowerSegmentSpillReload(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

getSelectionDAGInfo()

const SelectionDAGTargetInfo * RISCVSubtarget::getSelectionDAGInfo ( ) const

override

Definition at line 116 of file RISCVSubtarget.cpp.

References TSInfo.

getTailDupAggressiveThreshold()

unsigned llvm::RISCVSubtarget::getTailDupAggressiveThreshold ( ) const

inline

Definition at line 443 of file RISCVSubtarget.h.

getTargetABI()

RISCVABI::ABI llvm::RISCVSubtarget::getTargetABI ( ) const

inline

Definition at line 298 of file RISCVSubtarget.h.

Referenced by llvm::RISCV::getArgGPRs().

getTargetLowering()

const RISCVTargetLowering * llvm::RISCVSubtarget::getTargetLowering ( ) const

inlineoverride

Definition at line 164 of file RISCVSubtarget.h.

Referenced by getCallLowering(), and getInlineAsmLowering().

getUserReservedXRegs()

const std::bitset< 32 > & llvm::RISCVSubtarget::getUserReservedXRegs ( ) const

inline

Returns the X registers reserved by the reserve-xN features, indexed by N.

Aliases of these registers are not included.

Definition at line 302 of file RISCVSubtarget.h.

getVRGatherCostModel()

RISCVVRGatherCostModelEnum llvm::RISCVSubtarget::getVRGatherCostModel ( ) const

inline

Definition at line 187 of file RISCVSubtarget.h.

getXLen()

unsigned llvm::RISCVSubtarget::getXLen ( ) const

inline

Definition at line 242 of file RISCVSubtarget.h.

References is64Bit().

getXLenVT()

MVT llvm::RISCVSubtarget::getXLenVT ( ) const

inline

Definition at line 239 of file RISCVSubtarget.h.

References is64Bit().

Referenced by buildDefaultVLOps().

getZilsdAlign()

Align llvm::RISCVSubtarget::getZilsdAlign ( ) const

inline

Definition at line 257 of file RISCVSubtarget.h.

hasBEXTILike()

bool llvm::RISCVSubtarget::hasBEXTILike ( ) const

inline

Definition at line 221 of file RISCVSubtarget.h.

hasCLZLike()

bool llvm::RISCVSubtarget::hasCLZLike ( ) const

inline

Definition at line 207 of file RISCVSubtarget.h.

hasConditionalMoveFusion()

bool llvm::RISCVSubtarget::hasConditionalMoveFusion ( ) const

inline

Definition at line 223 of file RISCVSubtarget.h.

hasCPOPLike()

bool llvm::RISCVSubtarget::hasCPOPLike ( ) const

inline

Definition at line 211 of file RISCVSubtarget.h.

hasCTZLike()

bool llvm::RISCVSubtarget::hasCTZLike ( ) const

inline

Definition at line 208 of file RISCVSubtarget.h.

hasHalfFPLoadStoreMove()

bool llvm::RISCVSubtarget::hasHalfFPLoadStoreMove ( ) const

inline

Definition at line 203 of file RISCVSubtarget.h.

hasOptimizedSegmentLoadStore()

bool llvm::RISCVSubtarget::hasOptimizedSegmentLoadStore ( unsigned NF ) const

inline

Definition at line 344 of file RISCVSubtarget.h.

References llvm_unreachable.

hasREV8Like()

bool llvm::RISCVSubtarget::hasREV8Like ( ) const

inline

Definition at line 214 of file RISCVSubtarget.h.

hasREVLike()

bool llvm::RISCVSubtarget::hasREVLike ( ) const

inline

Definition at line 217 of file RISCVSubtarget.h.

hasShlAdd()

bool llvm::RISCVSubtarget::hasShlAdd ( int64_t ShAmt ) const

inline

Definition at line 229 of file RISCVSubtarget.h.

hasStdExtDOrZdinx()

bool llvm::RISCVSubtarget::hasStdExtDOrZdinx ( ) const

inline

Definition at line 198 of file RISCVSubtarget.h.

hasStdExtFOrZfinx()

bool llvm::RISCVSubtarget::hasStdExtFOrZfinx ( ) const

inline

Definition at line 197 of file RISCVSubtarget.h.

hasStdExtZfhminOrZhinxmin()

bool llvm::RISCVSubtarget::hasStdExtZfhminOrZhinxmin ( ) const

inline

Definition at line 200 of file RISCVSubtarget.h.

hasStdExtZfhOrZhinx()

bool llvm::RISCVSubtarget::hasStdExtZfhOrZhinx ( ) const

inline

Definition at line 199 of file RISCVSubtarget.h.

hasStdExtZvl()

bool llvm::RISCVSubtarget::hasStdExtZvl ( ) const

inline

Definition at line 196 of file RISCVSubtarget.h.

hasVInstructions()

bool llvm::RISCVSubtarget::hasVInstructions ( ) const

inline

Definition at line 327 of file RISCVSubtarget.h.

Referenced by llvm::RISCV::getArgVRs(), getELen(), getMaxInterleaveFactor(), getMaxRVVVectorSizeInBits(), getMinRVVVectorSizeInBits(), getScavSlotsNumForRVV(), and useRVVForFixedLengthVectors().

hasVInstructionsAnyF()

bool llvm::RISCVSubtarget::hasVInstructionsAnyF ( ) const

inline

Definition at line 338 of file RISCVSubtarget.h.

References hasVInstructionsF32().

hasVInstructionsBF16()

bool llvm::RISCVSubtarget::hasVInstructionsBF16 ( ) const

inline

Definition at line 336 of file RISCVSubtarget.h.

hasVInstructionsBF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsBF16Minimal ( ) const

inline

Definition at line 331 of file RISCVSubtarget.h.

hasVInstructionsF16()

bool llvm::RISCVSubtarget::hasVInstructionsF16 ( ) const

inline

Definition at line 330 of file RISCVSubtarget.h.

hasVInstructionsF16Minimal()

bool llvm::RISCVSubtarget::hasVInstructionsF16Minimal ( ) const

inline

Definition at line 329 of file RISCVSubtarget.h.

hasVInstructionsF32()

bool llvm::RISCVSubtarget::hasVInstructionsF32 ( ) const

inline

Definition at line 334 of file RISCVSubtarget.h.

Referenced by hasVInstructionsAnyF().

hasVInstructionsF64()

bool llvm::RISCVSubtarget::hasVInstructionsF64 ( ) const

inline

Definition at line 335 of file RISCVSubtarget.h.

hasVInstructionsFullMultiply()

bool llvm::RISCVSubtarget::hasVInstructionsFullMultiply ( ) const

inline

Definition at line 339 of file RISCVSubtarget.h.

hasVInstructionsI64()

bool llvm::RISCVSubtarget::hasVInstructionsI64 ( ) const

inline

Definition at line 328 of file RISCVSubtarget.h.

Referenced by getELen().

hasYInstructions()

bool llvm::RISCVSubtarget::hasYInstructions ( ) const

inline

Definition at line 193 of file RISCVSubtarget.h.

is64Bit()

bool llvm::RISCVSubtarget::is64Bit ( ) const

inline

Definition at line 237 of file RISCVSubtarget.h.

Referenced by llvm::RISCVRegisterInfo::getConstrainedRegClassForReg(), getXLen(), getXLenVT(), isCompressibleLoad(), isCompressibleStore(), isPExtPackedDoubleType(), isPExtPackedType(), isXRaySupported(), markSExt32Registers(), and selectRegImmLoadStoreOp().

isJumpExpensive()

bool llvm::RISCVSubtarget::isJumpExpensive ( ) const

inline

Definition at line 479 of file RISCVSubtarget.h.

isLittleEndian()

bool llvm::RISCVSubtarget::isLittleEndian ( ) const

inline

Definition at line 238 of file RISCVSubtarget.h.

Referenced by RISCVSubtarget().

isPExtPackedDoubleType()

bool RISCVSubtarget::isPExtPackedDoubleType

(

MVT

VT

)

const

Definition at line 171 of file RISCVSubtarget.cpp.

References is64Bit().

isPExtPackedType()

bool RISCVSubtarget::isPExtPackedType

(

MVT

VT

)

const

Definition at line 159 of file RISCVSubtarget.cpp.

References is64Bit().

isRegisterReservedByUser()

bool llvm::RISCVSubtarget::isRegisterReservedByUser ( Register i ) const

inlineoverride

Definition at line 305 of file RISCVSubtarget.h.

References assert(), getRegisterInfo(), llvm::Register::id(), and llvm::RISCVRegisterInfo::isRegisterReservedByUser().

isSoftFPABI()

bool llvm::RISCVSubtarget::isSoftFPABI ( ) const

inline

Definition at line 299 of file RISCVSubtarget.h.

References llvm::RISCVABI::isSoftFP().

Referenced by llvm::RISCV::getArgFPRs().

isTargetAndroid()

bool llvm::RISCVSubtarget::isTargetAndroid ( ) const

inline

Definition at line 402 of file RISCVSubtarget.h.

isTargetFuchsia()

bool llvm::RISCVSubtarget::isTargetFuchsia ( ) const

inline

Definition at line 403 of file RISCVSubtarget.h.

isXRaySupported()

bool llvm::RISCVSubtarget::isXRaySupported ( ) const

inlineoverride

Definition at line 322 of file RISCVSubtarget.h.

References is64Bit().

mirFileLoaded()

void RISCVSubtarget::mirFileLoaded ( MachineFunction & MF ) const

override

Definition at line 238 of file RISCVSubtarget.cpp.

References llvm::MachineFrameInfo::computeMaxCallFrameSize(), llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::isMaxCallFrameSizeComputed().

overridePostRASchedPolicy()

void RISCVSubtarget::overridePostRASchedPolicy ( MachineSchedPolicy & Policy, const SchedRegion & Region ) const

override

Definition at line 273 of file RISCVSubtarget.cpp.

References llvm::MISched::Bidirectional, llvm::MISched::BottomUp, getPostRASchedDirection(), llvm::MachineSchedPolicy::OnlyBottomUp, llvm::MachineSchedPolicy::OnlyTopDown, and llvm::MISched::TopDown.

overrideSchedPolicy()

void RISCVSubtarget::overrideSchedPolicy ( MachineSchedPolicy & Policy, const SchedRegion & Region ) const

override

Definition at line 257 of file RISCVSubtarget.cpp.

References llvm::MachineSchedPolicy::DisableLatencyHeuristic, llvm::MachineSchedPolicy::OnlyBottomUp, llvm::MachineSchedPolicy::OnlyTopDown, and llvm::MachineSchedPolicy::ShouldTrackPressure.

ParseSubtargetFeatures()

void llvm::RISCVSubtarget::ParseSubtargetFeatures	(	StringRef	CPU,
		StringRef	TuneCPU,
		StringRef	FS )

useAA()

bool RISCVSubtarget::useAA ( ) const

override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 250 of file RISCVSubtarget.cpp.

useConstantPoolForLargeInts()

bool RISCVSubtarget::useConstantPoolForLargeInts

(

)

const

Definition at line 154 of file RISCVSubtarget.cpp.

useDFAforSMS()

bool llvm::RISCVSubtarget::useDFAforSMS ( ) const

inlineoverride

Definition at line 420 of file RISCVSubtarget.h.

useMIPSCCMovInsn()

bool RISCVSubtarget::useMIPSCCMovInsn

(

)

const

Definition at line 292 of file RISCVSubtarget.cpp.

useMIPSLoadStorePairs()

bool RISCVSubtarget::useMIPSLoadStorePairs

(

)

const

Definition at line 288 of file RISCVSubtarget.cpp.

useRVVForFixedLengthVectors()

bool RISCVSubtarget::useRVVForFixedLengthVectors

(

)

const

Definition at line 227 of file RISCVSubtarget.cpp.

References getMinRVVVectorSizeInBits(), hasVInstructions(), and llvm::RISCV::RVVBitsPerBlock.

Member Data Documentation

CallLoweringInfo

std::unique_ptr<CallLowering> llvm::RISCVSubtarget::CallLoweringInfo

mutableprotected

Definition at line 381 of file RISCVSubtarget.h.

Referenced by getCallLowering().

InlineAsmLoweringInfo

std::unique_ptr<InlineAsmLowering> llvm::RISCVSubtarget::InlineAsmLoweringInfo

mutableprotected

Definition at line 385 of file RISCVSubtarget.h.

Referenced by getInlineAsmLowering().

InstSelector

std::unique_ptr<InstructionSelector> llvm::RISCVSubtarget::InstSelector

mutableprotected

Definition at line 382 of file RISCVSubtarget.h.

Referenced by getInstructionSelector().

Legalizer

std::unique_ptr<LegalizerInfo> llvm::RISCVSubtarget::Legalizer

mutableprotected

Definition at line 383 of file RISCVSubtarget.h.

Referenced by getLegalizerInfo().

RegBankInfo

std::unique_ptr<RISCVRegisterBankInfo> llvm::RISCVSubtarget::RegBankInfo

mutableprotected

Definition at line 384 of file RISCVSubtarget.h.

Referenced by getRegBankInfo().

TSInfo

std::unique_ptr<const SelectionDAGTargetInfo> llvm::RISCVSubtarget::TSInfo

protected

Definition at line 378 of file RISCVSubtarget.h.

Referenced by getSelectionDAGInfo(), and RISCVSubtarget().

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The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVSubtarget.h
• lib/Target/RISCV/RISCVSubtarget.cpp