RISCVSubtarget.h

Go to the documentation of this file.

//===-- RISCVSubtarget.h - Define Subtarget for the RISC-V ------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file declares the RISC-V specific subclass of TargetSubtargetInfo.
//
//===----------------------------------------------------------------------===//
 
#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H
 
#include "GISel/RISCVRegisterBankInfo.h"
#include "MCTargetDesc/RISCVBaseInfo.h"
#include "RISCVFrameLowering.h"
#include "RISCVISelLowering.h"
#include "RISCVInstrInfo.h"
#include "llvm/ADT/StringTable.h"
#include "llvm/CodeGen/GlobalISel/CallLowering.h"
#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Target/TargetMachine.h"
#include <bitset>
#include <cstdint>
#include <memory>
#include <optional>
 
#define OPTIONS_STRUCT_DECL
#include "RISCVOptions.inc"
 
#define GET_RISCV_MACRO_FUSION_PRED_DECL
#include "RISCVGenMacroFusion.inc"
 
#define GET_SUBTARGETINFO_HEADER
#include "RISCVGenSubtargetInfo.inc"
 
namespace llvm {
class StringRef;
 
namespace RISCVTuneInfoTable {
 
struct RISCVTuneInfo {
  StringTable::Offset Name;
  uint8_t PrefFunctionAlignment;
  uint8_t PrefLoopAlignment;
 
  // Information needed by LoopDataPrefetch.
  uint16_t CacheLineSize;
  uint16_t PrefetchDistance;
  uint16_t MinPrefetchStride;
  unsigned MaxPrefetchIterationsAhead;
 
  unsigned MinimumJumpTableEntries;
 
  // Tail duplication threshold at -O3.
  unsigned TailDupAggressiveThreshold;
 
  unsigned MaxStoresPerMemsetOptSize;
  unsigned MaxStoresPerMemset;
 
  unsigned MaxGluedStoresPerMemcpy;
  unsigned MaxStoresPerMemcpyOptSize;
  unsigned MaxStoresPerMemcpy;
 
  unsigned MaxStoresPerMemmoveOptSize;
  unsigned MaxStoresPerMemmove;
 
  unsigned MaxLoadsPerMemcmpOptSize;
  unsigned MaxLoadsPerMemcmp;
 
  // How many vector elements can be coalesced if on the
  // same cache line
  uint8_t MaxVectorCoalesceElts;
 
  // The direction of PostRA scheduling.
  MISched::Direction PostRASchedDirection;
 
  bool IsJumpExpensive;
};
 
#define GET_RISCVTuneInfoTable_DECL
#include "RISCVGenSearchableTables.inc"
} // namespace RISCVTuneInfoTable
 
class RISCVSubtarget : public RISCVGenSubtargetInfo {
public:
  // clang-format off
  enum RISCVProcFamilyEnum : uint8_t {
    Others,
    SiFive7,
    MIPSP8700,
    Andes45,
  };
  enum RISCVVRGatherCostModelEnum : uint8_t {
    Quadratic,
    NLog2N,
  };
  // clang-format on
private:
  const RISCVOptions &CLOpts;
 
  virtual void anchor();
 
  RISCVProcFamilyEnum RISCVProcFamily = Others;
  RISCVVRGatherCostModelEnum RISCVVRGatherCostModel = Quadratic;
 
  bool IsLittleEndian = true;
 
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
  bool ATTRIBUTE = DEFAULT;
#include "RISCVGenSubtargetInfo.inc"
 
  unsigned XSfmmTE = 0;
  unsigned ZvlLen = 0;
  unsigned RVVVectorBitsMin;
  unsigned RVVVectorBitsMax;
  uint8_t MaxInterleaveFactor = 2;
  RISCVABI::ABI TargetABI = RISCVABI::ABI::Unknown;
  // Set by the reserve-xN subtarget features, indexed by N. RISCVRegisterInfo
  // expands this to include aliases.
  std::bitset<32> UserReservedXRegs;
  const RISCVTuneInfoTable::RISCVTuneInfo *TuneInfo;
 
  RISCVFrameLowering FrameLowering;
  RISCVInstrInfo InstrInfo;
  RISCVTargetLowering TLInfo;
 
  /// Initializes using the passed in CPU and feature strings so that we can
  /// use initializer lists for subtarget initialization.
  RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,
                                                  StringRef CPU,
                                                  StringRef TuneCPU,
                                                  StringRef FS,
                                                  StringRef ABIName);
 
public:
  // Initializes the data members to match that of the specified triple.
  RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,
                 StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,
                 unsigned RVVVectorLMULMax, const TargetMachine &TM);
 
  ~RISCVSubtarget() override;
 
  // Parses features string setting specified subtarget options. The
  // definition of this function is auto-generated by tblgen.
  void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 
  const RISCVFrameLowering *getFrameLowering() const override {
    return &FrameLowering;
  }
  const RISCVOptions &getCLOpts() const { return CLOpts; }
  const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; }
  const RISCVRegisterInfo *getRegisterInfo() const override {
    return &InstrInfo.getRegisterInfo();
  }
  const RISCVTargetLowering *getTargetLowering() const override {
    return &TLInfo;
  }
 
  void mirFileLoaded(MachineFunction &MF) const override;
 
  bool enableMachineScheduler() const override { return true; }
 
  bool enablePostRAScheduler() const override { return UsePostRAScheduler; }
 
  Align getPrefFunctionAlignment() const {
    return Align(TuneInfo->PrefFunctionAlignment);
  }
  Align getPrefLoopAlignment() const {
    return Align(TuneInfo->PrefLoopAlignment);
  }
 
  /// Returns RISC-V processor family.
  /// Avoid this function! CPU specifics should be kept local to this class
  /// and preferably modeled with SubtargetFeatures or properties in
  /// initializeProperties().
  RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; }
 
  RISCVVRGatherCostModelEnum getVRGatherCostModel() const { return RISCVVRGatherCostModel; }
 
#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
  bool GETTER() const { return ATTRIBUTE; }
#include "RISCVGenSubtargetInfo.inc"
 
  bool hasYInstructions() const {
    return HasStdExtYCapMode || HasStdExtZyhybrid;
  }
  bool hasStdExtZvl() const { return ZvlLen != 0; }
  bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
  bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
  bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
  bool hasStdExtZfhminOrZhinxmin() const {
    return HasStdExtZfhmin || HasStdExtZhinxmin;
  }
  bool hasHalfFPLoadStoreMove() const {
    return HasStdExtZfhmin || HasStdExtZfbfmin;
  }
 
  bool hasCLZLike() const { return HasStdExtZbb || HasVendorXTHeadBb; }
  bool hasCTZLike() const {
    return HasStdExtZbb || (HasVendorXCVbitmanip && !IsRV64);
  }
  bool hasCPOPLike() const {
    return HasStdExtZbb || (HasVendorXCVbitmanip && !IsRV64);
  }
  bool hasREV8Like() const {
    return HasStdExtZbb || HasStdExtZbkb || HasVendorXTHeadBb;
  }
  bool hasREVLike() const {
    return HasStdExtP || ((HasVendorXCVbitmanip || HasVendorXqcibm) && !IsRV64);
  }
 
  bool hasBEXTILike() const { return HasStdExtZbs || HasVendorXTHeadBs; }
 
  bool hasConditionalMoveFusion() const {
    // Do we support fusing a branch+mv or branch+c.mv as a conditional move.
    return (hasConditionalCompressedMoveFusion() && hasStdExtZca()) ||
           hasShortForwardBranchIALU();
  }
 
  bool hasShlAdd(int64_t ShAmt) const {
    if (ShAmt <= 0)
      return false;
    if (ShAmt <= 3)
      return HasStdExtZba || HasVendorXAndesPerf || HasVendorXTHeadBa;
    return ShAmt <= 31 && HasVendorXqciac;
  }
 
  bool is64Bit() const { return IsRV64; }
  bool isLittleEndian() const { return IsLittleEndian; }
  MVT getXLenVT() const {
    return is64Bit() ? MVT::i64 : MVT::i32;
  }
  unsigned getXLen() const {
    return is64Bit() ? 64 : 32;
  }
  bool useMIPSLoadStorePairs() const;
  bool useMIPSCCMovInsn() const;
  unsigned getFLen() const {
    if (HasStdExtD)
      return 64;
 
    if (HasStdExtF)
      return 32;
 
    return 0;
  }
 
  Align getZilsdAlign() const {
    if (enableUnalignedScalarMem())
      return Align(1);
 
    if (allowZilsdWordAlign())
      return Align(4);
 
    return Align(8);
  }
 
  unsigned getELen() const {
    assert(hasVInstructions() && "Expected V extension");
    return hasVInstructionsI64() ? 64 : 32;
  }
  unsigned getRealMinVLen() const {
    unsigned VLen = getMinRVVVectorSizeInBits();
    return VLen == 0 ? ZvlLen : VLen;
  }
  unsigned getRealMaxVLen() const {
    unsigned VLen = getMaxRVVVectorSizeInBits();
    return VLen == 0 ? 65536 : VLen;
  }
  // If we know the exact VLEN, return it.  Otherwise, return std::nullopt.
  std::optional<unsigned> getRealVLen() const {
    unsigned Min = getRealMinVLen();
    if (Min != getRealMaxVLen())
      return std::nullopt;
    return Min;
  }
 
  /// If the ElementCount or TypeSize \p X is scalable and VScale (VLEN) is
  /// exactly known, returns \p X converted to a fixed quantity. Otherwise
  /// returns \p X unmodified.
  template <typename Quantity> Quantity expandVScale(Quantity X) const {
    if (auto VLen = getRealVLen(); VLen && X.isScalable()) {
      const unsigned VScale = *VLen / RISCV::RVVBitsPerBlock;
      X = Quantity::getFixed(X.getKnownMinValue() * VScale);
    }
    return X;
  }
 
  RISCVABI::ABI getTargetABI() const { return TargetABI; }
  bool isSoftFPABI() const { return RISCVABI::isSoftFP(TargetABI); }
  /// Returns the X registers reserved by the reserve-xN features, indexed by N.
  /// Aliases of these registers are not included.
  const std::bitset<32> &getUserReservedXRegs() const {
    return UserReservedXRegs;
  }
  bool isRegisterReservedByUser(Register i) const override {
    assert(i.id() < RISCV::NUM_TARGET_REGS && "Register out of range");
    return getRegisterInfo()->isRegisterReservedByUser(i.id());
  }
 
  TargetRegisterClass const *getLargestFPRegClass() const {
    if (HasStdExtQ)
      return &RISCV::FPR128RegClass;
    if (HasStdExtD)
      return &RISCV::FPR64RegClass;
    if (HasStdExtF)
      return &RISCV::FPR32RegClass;
    return nullptr;
  };
 
  // XRay support - require D and Zcf/Zcd extensions. Effectively D and C
  // without checking the C feature.
  bool isXRaySupported() const override {
    return hasStdExtD() && (is64Bit() || hasStdExtZcf()) && hasStdExtZcd();
  }
 
  // Vector codegen related methods.
  bool hasVInstructions() const { return HasStdExtZve32x; }
  bool hasVInstructionsI64() const { return HasStdExtZve64x; }
  bool hasVInstructionsF16Minimal() const { return HasStdExtZvfhmin; }
  bool hasVInstructionsF16() const { return HasStdExtZvfh; }
  bool hasVInstructionsBF16Minimal() const {
    return HasStdExtZvfbfmin || HasStdExtZvfbfa;
  }
  bool hasVInstructionsF32() const { return HasStdExtZve32f; }
  bool hasVInstructionsF64() const { return HasStdExtZve64d; }
  bool hasVInstructionsBF16() const { return HasStdExtZvfbfa; }
  // F16 and F64 both require F32.
  bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
  bool hasVInstructionsFullMultiply() const { return HasStdExtV; }
  unsigned getMaxInterleaveFactor() const {
    return hasVInstructions() ? MaxInterleaveFactor : 1;
  }
 
  bool hasOptimizedSegmentLoadStore(unsigned NF) const {
    switch (NF) {
    case 2:
      return hasOptimizedNF2SegmentLoadStore();
    case 3:
      return hasOptimizedNF3SegmentLoadStore();
    case 4:
      return hasOptimizedNF4SegmentLoadStore();
    case 5:
      return hasOptimizedNF5SegmentLoadStore();
    case 6:
      return hasOptimizedNF6SegmentLoadStore();
    case 7:
      return hasOptimizedNF7SegmentLoadStore();
    case 8:
      return hasOptimizedNF8SegmentLoadStore();
    default:
      llvm_unreachable("Unexpected NF");
    }
  }
 
  bool isPExtPackedType(MVT VT) const;
  bool isPExtPackedDoubleType(MVT VT) const;
 
  // Returns VLEN divided by DLEN. Where DLEN is the datapath width of the
  // vector hardware implementation which may be less than VLEN.
  unsigned getDLenFactor() const {
    if (DLenFactor2)
      return 2;
    return 1;
  }
 
protected:
  // SelectionDAGISel related APIs.
  std::unique_ptr<const SelectionDAGTargetInfo> TSInfo;
 
  // GlobalISel related APIs.
  mutable std::unique_ptr<CallLowering> CallLoweringInfo;
  mutable std::unique_ptr<InstructionSelector> InstSelector;
  mutable std::unique_ptr<LegalizerInfo> Legalizer;
  mutable std::unique_ptr<RISCVRegisterBankInfo> RegBankInfo;
  mutable std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
 
  // Return the known range for the bit length of RVV data registers as set
  // at the command line. A value of 0 means nothing is known about that particular
  // limit beyond what's implied by the architecture.
  // NOTE: Please use getRealMinVLen and getRealMaxVLen instead!
  unsigned getMaxRVVVectorSizeInBits() const;
  unsigned getMinRVVVectorSizeInBits() const;
 
public:
  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override;
  const CallLowering *getCallLowering() const override;
  InstructionSelector *getInstructionSelector() const override;
  const LegalizerInfo *getLegalizerInfo() const override;
  const RISCVRegisterBankInfo *getRegBankInfo() const override;
  const InlineAsmLowering *getInlineAsmLowering() const override;
 
  bool isTargetAndroid() const { return getTargetTriple().isAndroid(); }
  bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }
 
  bool useConstantPoolForLargeInts() const;
 
  // Maximum cost used for building integers, integers will be put into constant
  // pool if exceeded.
  unsigned getMaxBuildIntsCost() const;
 
  unsigned getMispredictionPenalty() const override;
  unsigned getLoadLatency() const override;
 
  bool useRVVForFixedLengthVectors() const;
 
  bool enableSubRegLiveness() const override;
 
  bool enableMachinePipeliner() const override;
 
  bool useDFAforSMS() const override { return false; }
 
  bool useAA() const override;
 
  unsigned getCacheLineSize() const override {
    return TuneInfo->CacheLineSize;
  };
  unsigned getPrefetchDistance() const override {
    return TuneInfo->PrefetchDistance;
  };
  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
                                unsigned NumStridedMemAccesses,
                                unsigned NumPrefetches,
                                bool HasCall) const override {
    return TuneInfo->MinPrefetchStride;
  };
  unsigned getMaxPrefetchIterationsAhead() const override {
    return TuneInfo->MaxPrefetchIterationsAhead;
  };
  bool enableWritePrefetching() const override { return true; }
 
  unsigned getMinimumJumpTableEntries() const;
 
  unsigned getTailDupAggressiveThreshold() const {
    return TuneInfo->TailDupAggressiveThreshold;
  }
 
  unsigned getMaxStoresPerMemset(bool OptSize) const {
    return OptSize ? TuneInfo->MaxStoresPerMemsetOptSize
                   : TuneInfo->MaxStoresPerMemset;
  }
 
  unsigned getMaxGluedStoresPerMemcpy() const {
    return TuneInfo->MaxGluedStoresPerMemcpy;
  }
 
  unsigned getMaxStoresPerMemcpy(bool OptSize) const {
    return OptSize ? TuneInfo->MaxStoresPerMemcpyOptSize
                   : TuneInfo->MaxStoresPerMemcpy;
  }
 
  unsigned getMaxStoresPerMemmove(bool OptSize) const {
    return OptSize ? TuneInfo->MaxStoresPerMemmoveOptSize
                   : TuneInfo->MaxStoresPerMemmove;
  }
 
  unsigned getMaxLoadsPerMemcmp(bool OptSize) const {
    return OptSize ? TuneInfo->MaxLoadsPerMemcmpOptSize
                   : TuneInfo->MaxLoadsPerMemcmp;
  }
 
  uint8_t getMaxVectorCoalesceElts() const {
    return TuneInfo->MaxVectorCoalesceElts;
  }
 
  MISched::Direction getPostRASchedDirection() const {
    return TuneInfo->PostRASchedDirection;
  }
 
  bool isJumpExpensive() const { return TuneInfo->IsJumpExpensive; }
 
  void overrideSchedPolicy(MachineSchedPolicy &Policy,
                           const SchedRegion &Region) const override;
 
  void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
                                 const SchedRegion &Region) const override;
};
} // namespace llvm
 
#endif