#include "RISCVISelLowering.h"#include "MCTargetDesc/RISCVMatInt.h"#include "RISCV.h"#include "RISCVConstantPoolValue.h"#include "RISCVMachineFunctionInfo.h"#include "RISCVRegisterInfo.h"#include "RISCVSelectionDAGInfo.h"#include "RISCVSubtarget.h"#include "RISCVVectorUtils.h"#include "llvm/ADT/SmallSet.h"#include "llvm/ADT/SmallVector.h"#include "llvm/ADT/Statistic.h"#include "llvm/Analysis/MemoryLocation.h"#include "llvm/Analysis/ValueTracking.h"#include "llvm/Analysis/VectorUtils.h"#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"#include "llvm/CodeGen/MachineFrameInfo.h"#include "llvm/CodeGen/MachineFunction.h"#include "llvm/CodeGen/MachineInstrBuilder.h"#include "llvm/CodeGen/MachineJumpTableInfo.h"#include "llvm/CodeGen/MachineRegisterInfo.h"#include "llvm/CodeGen/SDPatternMatch.h"#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"#include "llvm/CodeGen/ValueTypes.h"#include "llvm/IR/DiagnosticInfo.h"#include "llvm/IR/DiagnosticPrinter.h"#include "llvm/IR/IRBuilder.h"#include "llvm/IR/Instructions.h"#include "llvm/IR/IntrinsicInst.h"#include "llvm/IR/IntrinsicsRISCV.h"#include "llvm/MC/MCCodeEmitter.h"#include "llvm/MC/MCInstBuilder.h"#include "llvm/Support/ErrorHandling.h"#include "llvm/Support/InstructionCost.h"#include "llvm/Support/KnownBits.h"#include "llvm/Support/MathExtras.h"#include <optional>#include "RISCVGenAsmMatcher.inc"#include "RISCVGenSearchableTables.inc"Go to the source code of this file.
Classes | |
| struct | VIDSequence |
Namespaces | |
| namespace | llvm |
| This is an optimization pass for GlobalISel generic memory operations. | |
| namespace | llvm::RISCVVIntrinsicsTable |
Macros | |
| #define | DEBUG_TYPE "riscv-lower" |
| #define | OP_CASE(NODE) |
| #define | VP_CASE(NODE) |
| #define | CC_VLS_CASE(ABI_VLEN) |
| #define | GET_REGISTER_MATCHER |
| #define | GET_RISCVVIntrinsicsTable_IMPL |
Variables | |
| static const unsigned | ZvfbfaOps [] |
| const uint64_t | ModeMask64 = ~RISCVExceptFlags::ALL |
| const uint32_t | ModeMask32 = ~RISCVExceptFlags::ALL |
| static auto | m_ReverseEVL |
| Matches a reverse shifted right EVL elements, or a vp.reverse. | |
Macro Definition Documentation
◆ CC_VLS_CASE
| #define CC_VLS_CASE | ( | ABI_VLEN | ) |
◆ DEBUG_TYPE
| #define DEBUG_TYPE "riscv-lower" |
Definition at line 55 of file RISCVISelLowering.cpp.
◆ GET_REGISTER_MATCHER
| #define GET_REGISTER_MATCHER |
Definition at line 30953 of file RISCVISelLowering.cpp.
◆ GET_RISCVVIntrinsicsTable_IMPL
| #define GET_RISCVVIntrinsicsTable_IMPL |
Definition at line 31198 of file RISCVISelLowering.cpp.
◆ OP_CASE
| #define OP_CASE | ( | NODE | ) |
Referenced by getRISCVVLOp().
◆ VP_CASE
| #define VP_CASE | ( | NODE | ) |
Referenced by getRISCVVLOp().
Function Documentation
◆ canonicalizeMaskForVLPredicate()
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Given.
in which the SETCC's condition code could be (U)LT or (U)GT. We can turn it into
where the SETCC's condition code is also canonicalized into (U)LT; The idea behind this canonicalization is that if p is used as a mask in a masked.load/store, we can easily turn it to use VL-predicate later by assigning vl = min(m, <number of vector elements>).
Definition at line 21382 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::KnownBits::add(), llvm::cast(), CC, llvm::SelectionDAG::computeKnownBits(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtOrTrunc(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCSwappedOperands(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getStepVector(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isFixedLengthVector(), llvm::ISD::isSignedIntSetCC(), LHS, llvm::PatternMatch::m_NSWAddLike(), llvm::PatternMatch::m_NUWAddLike(), llvm::PatternMatch::m_Value(), llvm::SDNodeFlags::NoSignedWrap, llvm::SDNodeFlags::NoUnsignedWrap, llvm::Offset, RHS, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULT, llvm::ISD::SMIN, llvm::ISD::SUB, std::swap(), uint64_t, llvm::ISD::UMIN, and llvm::SelectionDAG::willNotOverflowAdd().
Referenced by performSETCCCombine().
◆ canonicalizeVSelectTrueToOneUse()
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Definition at line 24255 of file RISCVISelLowering.cpp.
References CC, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SelectionDAG::isSplatValue(), N, SDValue(), llvm::ISD::SETCC, llvm::ISD::SPLAT_VECTOR_PARTS, Subtarget, and llvm::ISD::VSELECT.
Referenced by performVSELECTCombine().
◆ combine_CC()
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Definition at line 23971 of file RISCVISelLowering.cpp.
References llvm::all_of(), llvm::ISD::AND, llvm::cast(), CC, llvm::ISD::Constant, DL, llvm::dyn_cast(), llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueSizeInBits(), llvm::isa(), llvm::isInt(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::isPowerOf2_64(), LHS, llvm::Log2_64(), llvm::SelectionDAG::MaskedValueIsZero(), RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, Subtarget, translateSetCCForBranch(), tryDemorganOfBooleanCondition(), uint64_t, and llvm::ISD::XOR.
◆ combineAddMulh()
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Definition at line 19685 of file RISCVISelLowering.cpp.
References A(), B(), C(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::Hi, llvm::EVT::isSimple(), Lo, llvm::PatternMatch::m_Add(), llvm::PatternMatch::m_BinOp(), llvm::SDPatternMatch::m_ConstInt(), llvm::PatternMatch::m_Deferred(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Value(), llvm::ISD::MULHS, N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::SelectionDAG::SplitVector(), llvm::ISD::SRL, Subtarget, TLI, llvm::ISD::TRUNCATE, and X.
Referenced by performADDCombine().
◆ combineAddMulParts()
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Definition at line 19750 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), getRVPMulPartsAccIntrinsic(), llvm::SelectionDAG::getTargetConstant(), I, llvm::ISD::INTRINSIC_WO_CHAIN, Mul, N, llvm::Intrinsic::not_intrinsic, SDValue(), and Subtarget.
Referenced by performADDCombine().
◆ combineAddOfBooleanXor()
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Definition at line 19650 of file RISCVISelLowering.cpp.
References DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getNegative(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, SDValue(), and llvm::ISD::XOR.
Referenced by performADDCombine().
◆ combineAddOfExts()
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Definition at line 19618 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::isVector(), llvm::PatternMatch::m_Add(), llvm::MIPatternMatch::m_OneUse(), llvm::SDPatternMatch::m_SpecificVT(), llvm::SDPatternMatch::m_UnaryOp(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExtOrSExt(), N, llvm::SDPatternMatch::sd_match(), SDValue(), Subtarget, and X.
Referenced by performADDCombine().
◆ combineAddOfExtsAlreadyExtended()
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Definition at line 19511 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::Add, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::Use::getOperandNo(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::Use::getUser(), llvm::SDValue::getValueType(), llvm::SelectionDAG::isSplatValue(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), LHS, llvm::ISD::MUL, N, RHS, SDValue(), llvm::ISD::SIGN_EXTEND, Subtarget, llvm::ISD::VECREDUCE_ADD, llvm::SelectionDAG::willNotOverflowAdd(), and llvm::ISD::ZERO_EXTEND.
Referenced by performADDCombine().
◆ combineAddPackedByteDot()
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Definition at line 19774 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BUILD_VECTOR, DL, llvm::SelectionDAG::getExtractVectorElt(), llvm::SelectionDAG::getNode(), llvm::Hi, I, Lo, llvm::SDPatternMatch::m_Node(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Value(), N, Opc, llvm::SDPatternMatch::sd_match(), SDValue(), and Subtarget.
Referenced by performADDCombine().
◆ combineBinOpOfExt()
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Definition at line 19569 of file RISCVISelLowering.cpp.
References C(), llvm::SelectionDAG::getContext(), llvm::EVT::getHalfSizedIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SUB, llvm::ISD::UDIV, llvm::ISD::UREM, and llvm::ISD::ZERO_EXTEND.
Referenced by performADDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performMULCombine(), and performSUBCombine().
◆ combineBinOpOfExtractToReduceTree()
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Perform two related transforms whose purpose is to incrementally recognize an explode_vector followed by scalar reduction as a vector reduction node.
This exists to recover from a deficiency in SLP which can't handle forests with multiple roots sharing common nodes. In some cases, one of the trees will be vectorized, and the other will remain (unprofitably) scalarized.
Definition at line 19034 of file RISCVISelLowering.cpp.
References assert(), llvm::cast(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getExtractSubvector(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::ISD::getVecReduceBaseOpcode(), getVecReduceOpcode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::EVT::isInteger(), llvm::isNullConstant(), llvm::EVT::isScalableVector(), LHS, N, llvm::SelectionDAG::NewNodesMustHaveLegalTypes, Opc, RHS, SDValue(), Subtarget, std::swap(), and uint64_t.
Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().
◆ combineBinOpToReduce()
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Definition at line 19137 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, llvm::ISD::AND, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::SelectionDAG::isIdentityElement(), isNonZeroAVL(), llvm::isNullConstant(), llvm::SDNode::isUndef(), llvm_unreachable, lowerScalarInsert(), N, Opc, llvm::ISD::OR, SDValue(), llvm::ISD::SMAX, llvm::ISD::SMIN, Subtarget, llvm::ISD::UMAX, llvm::ISD::UMIN, V, and llvm::ISD::XOR.
Referenced by performADDCombine(), performANDCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performORCombine(), and performXORCombine().
◆ combineDeMorganOfBoolean()
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Definition at line 20227 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isOneConstant(), llvm::SelectionDAG::MaskedValueIsZero(), N, Opc, llvm::ISD::OR, SDValue(), and llvm::ISD::XOR.
Referenced by performANDCombine(), and performORCombine().
◆ combineMinMaxToSat()
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Definition at line 25330 of file RISCVISelLowering.cpp.
References llvm::APInt::countr_one(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SDValue::getConstantOperandAPInt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), N, SDValue(), llvm::ISD::SMAX, llvm::ISD::SMIN, Subtarget, and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineNarrowableShiftedLoad()
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Definition at line 20529 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::EVT::getSizeInBits(), llvm::APInt::getZExtValue(), llvm::EVT::isScalarInteger(), llvm::APInt::lshr(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Shl(), llvm::SDPatternMatch::m_SpecificOpc(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SHL, and uint64_t.
Referenced by performANDCombine().
◆ combineNegOfSelectCCSubs()
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Definition at line 20142 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isNullConstant(), llvm::PatternMatch::m_Specific(), llvm::PatternMatch::m_Sub(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), X, and Y.
Referenced by performSUBCombine().
◆ combineOp_VLToVWOp_VL()
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Combine a binary or FMA operation to its equivalent VW or VW_W form.
The supported combines are: add | add_vl | or disjoint | or_vl disjoint -> vwadd(u) | vwadd(u)_w sub | sub_vl -> vwsub(u) | vwsub(u)_w mul | mul_vl -> vwmul(u) | vwmul_su shl | shl_vl -> vwsll fadd_vl -> vfwadd | vfwadd_w fsub_vl -> vfwsub | vfwsub_w fmul_vl -> vfwmul vwadd_w(u) -> vwadd(u) vwsub_w(u) -> vwsub(u) vfwadd_w -> vfwadd vfwsub_w -> vfwsub
Definition at line 22610 of file RISCVISelLowering.cpp.
References assert(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SmallPtrSetImpl< PtrType >::contains(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::Use::getOperandNo(), llvm::Use::getUser(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LHS, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), RHS, SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), Subtarget, and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine(), performSHLCombine(), performVFMADD_VLCombine(), and performVWADDSUBW_VLCombine().
◆ combineOrAndToBitfieldInsert()
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Definition at line 20731 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::sampleprof::Base, llvm::SelectionDAG::computeKnownBits(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::APInt::getZExtValue(), llvm::APInt::isSubsetOf(), llvm::Known, llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Or(), llvm::PatternMatch::m_Shl(), llvm::SDPatternMatch::m_SpecificVT(), llvm::PatternMatch::m_Value(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::SDPatternMatch::sd_match(), SDValue(), Subtarget, and llvm::APInt::ugt().
Referenced by performORCombine().
◆ combineOrOfCZERO()
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Definition at line 20616 of file RISCVISelLowering.cpp.
References assert(), Cond, llvm::SDNodeFlags::Disjoint, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isOneConstant(), N, llvm::ISD::OR, SDValue(), and llvm::ISD::XOR.
Referenced by performORCombine().
◆ combineOrToBitfieldInsert()
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Definition at line 20691 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), llvm::APInt::isShiftedMask(), llvm::APInt::isSignedIntN(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Or(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), Subtarget, and X.
Referenced by performORCombine().
◆ combinePExtTruncate()
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Definition at line 20276 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, B(), llvm::ISD::BUILD_VECTOR, C(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getExtractVectorElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getZExtValue(), llvm::Hi, llvm::isConstOrConstSplat(), llvm::EVT::isVector(), LHS, Lo, llvm::ISD::MUL, N, Opc, RHS, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SRL, Subtarget, std::swap(), and llvm::ISD::ZERO_EXTEND.
Referenced by performTRUNCATECombine().
◆ combinePExtWideningAddAcc()
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Definition at line 19869 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, llvm::Add, B(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getValueType(), High, llvm::Low, llvm::PatternMatch::m_Add(), llvm::SDPatternMatch::m_Node(), llvm::MIPatternMatch::m_OneUse(), llvm::SDPatternMatch::m_SpecificVT(), llvm::PatternMatch::m_Value(), N, Opc, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, Subtarget, V, and llvm::ISD::ZERO_EXTEND.
Referenced by performADDCombine().
◆ combinePExtWideningAddSub()
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Definition at line 19806 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, B(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getValueType(), llvm::SDValue::hasOneUse(), High, llvm::Low, N, Opc, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SUB, Subtarget, and llvm::ISD::ZERO_EXTEND.
Referenced by performADDCombine(), and performSUBCombine().
◆ combinePExtWideningMul()
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Definition at line 21176 of file RISCVISelLowering.cpp.
References A(), B(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::hasOneUse(), N, SDValue(), llvm::ISD::SIGN_EXTEND, Subtarget, std::swap(), Zero, and llvm::ISD::ZERO_EXTEND.
Referenced by performMULCombine().
◆ combinePExtWideningSubAcc()
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Definition at line 19948 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, B(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getValueType(), High, llvm::Low, llvm::PatternMatch::m_Add(), llvm::SDPatternMatch::m_AnyOf(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_SExt(), llvm::SDPatternMatch::m_SpecificVT(), llvm::PatternMatch::m_Sub(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExt(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SUB, Subtarget, and llvm::ISD::ZERO_EXTEND.
Referenced by performSUBCombine().
◆ combineSelectAndUse()
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Definition at line 19360 of file RISCVISelLowering.cpp.
References llvm::AllOnes, llvm::ISD::AND, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::isNullConstant(), llvm::EVT::isVector(), isZeroOrAllOnes(), N, SDValue(), llvm::ISD::SELECT, Subtarget, and std::swap().
◆ combineSelectAndUseCommutative()
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Definition at line 19423 of file RISCVISelLowering.cpp.
References llvm::AllOnes, combineSelectAndUse(), N, SDValue(), and Subtarget.
◆ combineShlAddIAdd()
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Definition at line 19328 of file RISCVISelLowering.cpp.
References combineShlAddIAddImpl(), N, llvm::Other, SDValue(), Subtarget, and V.
Referenced by performADDCombine().
◆ combineShlAddIAddImpl()
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Definition at line 19289 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::isa(), llvm::PatternMatch::m_Add(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Shl(), llvm::PatternMatch::m_Value(), N, llvm::Other, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::APInt::sgt(), llvm::APInt::slt(), uint64_t, and llvm::SDNode::use_size().
Referenced by combineShlAddIAdd().
◆ combineSubOfBoolean()
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Definition at line 20043 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getOperandCondCode(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isInteger(), llvm::isOneConstant(), llvm::APInt::isSignedIntN(), N, SDValue(), llvm::ISD::SETCC, and llvm::ISD::XOR.
Referenced by performSUBCombine().
◆ combineSubShiftToOrcB()
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Definition at line 20087 of file RISCVISelLowering.cpp.
References llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::APInt::getSplat(), llvm::SDValue::hasOneUse(), llvm::SelectionDAG::MaskedValueIsZero(), N, SDValue(), llvm::ISD::SHL, llvm::ISD::SRL, and Subtarget.
Referenced by performSUBCombine().
◆ combineToVCPOP()
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Definition at line 25183 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::RISCVTargetLowering::computeVLMAX(), ContainerVT, convertToScalableVector(), llvm::ISD::CTPOP, DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::EVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::MVT::isFixedLengthVector(), llvm::EVT::isScalarInteger(), llvm::EVT::isSimple(), llvm::MVT::isVectorOf(), llvm::Log2_32(), N, Opc, SDValue(), Subtarget, TLI, llvm::ISD::VECREDUCE_ADD, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineToVWMACC()
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Definition at line 24880 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, assert(), DL, getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SDValue::isUndef(), N, Opc, SDValue(), Subtarget, and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineTruncOfSraSext()
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Definition at line 25126 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::EVT::isVector(), isVLMax(), N, SDValue(), llvm::ISD::SIGN_EXTEND, llvm::ISD::SMIN, llvm::SMin, llvm::ISD::SRA, V, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineVdot4aAccum()
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Definition at line 24945 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, assert(), DL, getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::isUndef(), N, Opc, SDValue(), Subtarget, and std::swap().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineVectorMulToSraBitcast()
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Definition at line 21140 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::ISD::isConstantSplatVector(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SRA, llvm::ISD::SRL, TLI, llvm::V1, and llvm::V3.
Referenced by performMULCombine().
◆ combineVectorSizedSetCCEquality()
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Try to map an integer comparison with size > XLEN to vector instructions before type legalization splits it up into chunks.
Definition at line 21473 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, CC, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::Use::getUser(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::Function::hasFnAttribute(), llvm::MVT::INVALID_SIMPLE_VALUE_TYPE, llvm::isa(), llvm::EVT::isByteSized(), llvm::EVT::isInteger(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::EVT::isScalarInteger(), llvm::EVT::isSimple(), llvm::EVT::isVector(), llvm::ISD::LOAD, llvm::peekThroughBitcasts(), SDValue(), llvm::ISD::SETNE, Subtarget, V, llvm::ISD::VECREDUCE_OR, X, and Y.
Referenced by combineSetCC(), performSETCCCombine(), and performSETCCCombine().
◆ combineVFMADD_VLWithVFNEG_VL()
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Definition at line 23688 of file RISCVISelLowering.cpp.
References A(), B(), C(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SelectionDAGTargetInfo::isTargetStrictFPOpcode(), N, negateFMAOpcode(), llvm::Offset, SDValue(), and V.
Referenced by performVFMADD_VLCombine().
◆ combineVMNOTOfSetCC()
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Definition at line 20825 of file RISCVISelLowering.cpp.
References CC, llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCInverse(), N, and SDValue().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ combineVWADDSUBWSelect()
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Definition at line 22727 of file RISCVISelLowering.cpp.
References assert(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVectorAllZeros(), llvm::isNullOrNullSplat(), llvm::SDValue::isUndef(), N, Opc, SDValue(), llvm::ISD::VSELECT, X, and Y.
Referenced by performVWADDSUBW_VLCombine().
◆ combineXorToBitfieldInsert()
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Definition at line 20655 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::sampleprof::Base, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::APInt::isShiftedMask(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::PatternMatch::m_Deferred(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Xor(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SRA, and Subtarget.
Referenced by performXORCombine().
◆ compressShuffleOfShuffles()
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Definition at line 5693 of file RISCVISelLowering.cpp.
References llvm::cast(), DL, llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVectorShuffle(), llvm::SDValue::hasOneUse(), SDValue(), llvm::seq(), Subtarget, llvm::V1, and llvm::ISD::VECTOR_SHUFFLE.
Referenced by performVECTOR_SHUFFLECombine().
◆ computeGREVOrGORC()
Definition at line 27299 of file RISCVISelLowering.cpp.
References uint64_t.
Referenced by llvm::RISCVTargetLowering::computeKnownBitsForTargetInstr(), llvm::RISCVTargetLowering::computeKnownBitsForTargetNode(), and llvm::RISCVTargetLowering::SimplifyDemandedBitsForTargetNode().
◆ convertFromScalableVector()
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Definition at line 3435 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getExtractSubvector(), llvm::EVT::isFixedLengthVector(), Subtarget, and V.
◆ convertLocVTToValVT()
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Definition at line 28520 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertFromScalableVector(), DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), llvm_unreachable, llvm::CCValAssign::needsCustom(), and Subtarget.
◆ convertToScalableVector()
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Definition at line 3424 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::isScalableVector(), Subtarget, and V.
◆ convertValVTToLocVT()
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Definition at line 28582 of file RISCVISelLowering.cpp.
References llvm::CCValAssign::BCvt, llvm::ISD::BITCAST, convertToScalableVector(), DL, llvm::CCValAssign::Full, llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getNode(), llvm::CCValAssign::getValVT(), llvm::MVT::isFixedLengthVector(), llvm::EVT::isInteger(), llvm::EVT::isScalableVector(), llvm_unreachable, llvm::CCValAssign::needsCustom(), and Subtarget.
◆ customLegalizeToWOp()
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Definition at line 17119 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), getRISCVWOpcode(), N, and llvm::ISD::TRUNCATE.
◆ customLegalizeToWOpWithSExt()
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Definition at line 17132 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), N, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::TRUNCATE.
◆ emitBuildPairF64Pseudo()
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Definition at line 27840 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOStore, Register, Subtarget, std::swap(), and TII.
◆ emitFROUND()
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Definition at line 28255 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), F, I, llvm_unreachable, MBB, MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), llvm::MachineBasicBlock::splice(), Subtarget, TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ EmitLoweredCascadedSelect()
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Definition at line 27923 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::First, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVCC::getBrCond(), llvm::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::splice(), Subtarget, TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by emitSelectPseudo().
◆ emitQuietFCMP()
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Definition at line 27886 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), MI, MRI, llvm::MachineInstr::NoFPExcept, llvm::MachineInstr::setFlag(), Subtarget, and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ emitReadCounterWidePseudo()
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Definition at line 27736 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineFunction::CreateMachineBasicBlock(), DL, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getBasicBlock(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineFunction::insert(), MI, llvm::MachineBasicBlock::splice(), TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ emitSelectPseudo()
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Definition at line 28026 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::any_of(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), CC, llvm::MachineInstr::collectDebugValues(), llvm::SmallSet< T, N, C >::count(), DL, E(), EmitLoweredCascadedSelect(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), F, llvm::MachineBasicBlock::getBasicBlock(), llvm::RISCVCC::getBrCond(), llvm::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), I, llvm::SmallSet< T, N, C >::insert(), llvm::MachineBasicBlock::instr_end(), LHS, MI, llvm::Next, llvm::next_nodbg(), llvm::MachineBasicBlock::push_back(), RHS, llvm::MachineBasicBlock::setCallFrameSize(), llvm::MachineBasicBlock::splice(), Subtarget, TII, and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().
◆ emitSplitF64Pseudo()
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Definition at line 27801 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), assert(), llvm::BuildMI(), DL, llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getSubtarget(), llvm::MachinePointerInfo::getWithOffset(), MI, llvm::MachineMemOperand::MOLoad, Subtarget, std::swap(), and TII.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ emitVFROUND_NOEXCEPT_MASK()
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Definition at line 28192 of file RISCVISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::RISCVII::getLMul(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::RISCVII::getSEWOpNum(), llvm::MachineFunction::getSubtarget(), lookupMaskedIntrinsic(), llvm::RISCV::RISCVMaskedPseudoInfo::MaskedPseudo, MI, MRI, TII, and TRI.
Referenced by llvm::RISCVTargetLowering::EmitInstrWithCustomInserter().
◆ expandMul()
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Definition at line 21039 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::countr_zero(), DL, llvm::dyn_cast(), expandMulToAddOrSubOfShl(), expandMulToNAFSequence(), expandMulToShlAddShlAdd(), llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::ConstantSDNode::getZExtValue(), llvm::Function::hasMinSize(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isInt(), llvm::isPowerOf2_64(), llvm::Log2_64(), N, llvm::Offset, SDValue(), llvm::ISD::SHL, llvm::ISD::SUB, Subtarget, uint64_t, V, and X.
Referenced by performMULCombine().
◆ expandMulToAddOrSubOfShl()
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Definition at line 20931 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isPowerOf2_64(), llvm::Log2_64(), llvm::SDPatternMatch::m_ExactSr(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SHL, llvm::ISD::SUB, uint64_t, and X.
Referenced by expandMul().
◆ expandMulToNAFSequence()
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Definition at line 20906 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::BitWidth, DL, E(), llvm::SelectionDAG::getConstant(), llvm::EVT::getFixedSizeInBits(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getShiftAmountConstant(), I, N, llvm::ISD::SHL, llvm::ISD::SUB, and uint64_t.
Referenced by expandMul().
◆ expandMulToShlAddShlAdd()
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Definition at line 20992 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getShlAddShlAdd(), llvm::SelectionDAG::getTargetConstant(), llvm::isShifted359(), N, SDValue(), llvm::ISD::SHL, uint64_t, and X.
Referenced by expandMul().
◆ foldBinOpIntoSelectIfProfitable()
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Definition at line 10555 of file RISCVISelLowering.cpp.
References DL, llvm::dyn_cast(), llvm::SelectionDAG::FoldConstantArithmetic(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSelect(), llvm::SDNode::getValueType(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::APInt::isAllOnes(), llvm::ConstantSDNode::isOpaque(), llvm::APInt::isZero(), SDValue(), llvm::ISD::SELECT, Subtarget, and std::swap().
◆ foldConcatVector()
If concat_vector(V1,V2) could be folded away to some existing vector source, return it.
Note that the source may be larger than the requested concat_vector (i.e. a extract_subvector might be required.)
Definition at line 5348 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::isScalableVector(), SDValue(), and llvm::V1.
Referenced by getSingleShuffleSrc(), and lowerVECTOR_SHUFFLEAsRV32PNarrowingShift().
◆ foldReduceOperandViaVDOT4A()
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Definition at line 24517 of file RISCVISelLowering.cpp.
References A(), B(), DL, foldReduceOperandViaVDOT4A(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), getQDOTXResultType(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), getZeroPaddedAdd(), llvm::ISD::isExtOpcode(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf(), llvm::PatternMatch::m_AddLike(), llvm::PatternMatch::m_Mul(), llvm::PatternMatch::m_Value(), Opc, llvm::ISD::PARTIAL_REDUCE_SMLA, llvm::ISD::PARTIAL_REDUCE_SUMLA, llvm::ISD::PARTIAL_REDUCE_UMLA, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SIGN_EXTEND, Subtarget, std::swap(), TLI, and llvm::ISD::ZERO_EXTEND.
Referenced by foldReduceOperandViaVDOT4A(), and performVECREDUCECombine().
◆ foldSelectOfCTTZOrCTLZ()
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Definition at line 24161 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::BitWidth, Cond, llvm::ISD::CTLZ, llvm::ISD::CTLZ_ZERO_POISON, llvm::ISD::CTTZ, llvm::ISD::CTTZ_ZERO_POISON, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::isNullConstant(), llvm::isPowerOf2_32(), N, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by performSELECTCombine().
◆ foldSelectToUSATI()
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Definition at line 24352 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsGE(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::isScalarInteger(), llvm::MIPatternMatch::m_AllOnes(), llvm::PatternMatch::m_Select(), llvm::PatternMatch::m_SExt(), llvm::PatternMatch::m_Specific(), llvm::PatternMatch::m_SpecificInt(), llvm::SDPatternMatch::m_SpecificSetCC(), llvm::SDPatternMatch::m_SpecificVT(), llvm::PatternMatch::m_Trunc(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SETGT, llvm::ISD::SETUGT, llvm::ISD::SIGN_EXTEND, Subtarget, llvm::ISD::TRUNCATE, and uint64_t.
Referenced by performSELECTCombine().
◆ getAllOnesMask()
Creates an all ones mask suitable for masking a vector of type VecTy with vector length VL.
Definition at line 3456 of file RISCVISelLowering.cpp.
References DL, getMaskTypeFor(), and llvm::SelectionDAG::getNode().
Referenced by getDefaultScalableVLOps(), getDefaultVLOps(), and lowerVectorIntrinsicScalars().
◆ getContainerForFixedLengthVector()
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Definition at line 3383 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::getScalableVectorVT(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), llvm::isPowerOf2_32(), llvm_unreachable, llvm::RISCV::RVVBitsPerBlock, llvm::MVT::SimpleTy, Subtarget, and useRVVForFixedLengthVectorVT().
◆ getDefaultScalableVLOps()
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Definition at line 3463 of file RISCVISelLowering.cpp.
References assert(), DL, getAllOnesMask(), llvm::SelectionDAG::getRegister(), llvm::MVT::isScalableVector(), and Subtarget.
Referenced by combineToVWMACC(), combineVdot4aAccum(), getDefaultVLOps(), and performSHLCombine().
◆ getDefaultVLOps() [1/2]
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Definition at line 3485 of file RISCVISelLowering.cpp.
References assert(), ContainerVT, DL, getDefaultScalableVLOps(), getDefaultVLOps(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), and Subtarget.
◆ getDefaultVLOps() [2/2]
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Definition at line 3472 of file RISCVISelLowering.cpp.
References assert(), ContainerVT, DL, getAllOnesMask(), llvm::SelectionDAG::getConstant(), Subtarget, and uint64_t.
Referenced by combineToVCPOP(), getDefaultVLOps(), getWideningInterleave(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaVID(), lowerCONVERT_FROM_ARBITRARY_FP(), lowerCttzElts(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlidedown(), lowerVECTOR_SHUFFLEAsVSlideup(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), lowerZvzipVPAIR(), lowerZvzipVUNZIP(), lowerZvzipVZIP(), matchSplatAsGather(), performFP_TO_INTCombine(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getDeinterleaveShiftAndTrunc()
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Definition at line 5500 of file RISCVISelLowering.cpp.
References llvm::MVT::changeVectorElementType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getInsertSubvector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::ISD::SRL, and llvm::ISD::TRUNCATE.
◆ getExactInteger()
Definition at line 4091 of file RISCVISelLowering.cpp.
References llvm::BitWidth, llvm::APFloat::convertToInteger(), llvm::APInt::extractBits(), llvm::APFloatBase::opInvalidOp, and llvm::TowardZero.
Referenced by isSimpleVIDSequence().
◆ getIntrinsicForMaskedAtomicRMWBinOp()
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Definition at line 30175 of file RISCVISelLowering.cpp.
References llvm::AtomicRMWInst::Add, llvm_unreachable, llvm::AtomicRMWInst::Max, llvm::AtomicRMWInst::Min, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::UMax, llvm::AtomicRMWInst::UMin, and llvm::AtomicRMWInst::Xchg.
◆ getLargeExternalSymbol()
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Definition at line 10168 of file RISCVISelLowering.cpp.
References llvm::RISCVConstantPoolValue::Create(), DL, llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), and N.
Referenced by llvm::RISCVTargetLowering::LowerCall().
◆ getLargeGlobalAddress()
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Definition at line 10158 of file RISCVISelLowering.cpp.
References llvm::RISCVConstantPoolValue::Create(), DL, llvm::MachinePointerInfo::getConstantPool(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstantPool(), and N.
Referenced by llvm::RISCVTargetLowering::LowerCall().
◆ getLMULOctuple()
Definition at line 5386 of file RISCVISelLowering.cpp.
References assert(), ContainerVT, llvm::isPowerOf2_32(), and llvm::RISCV::RVVBitsPerBlock.
Referenced by isLegalVTForZvzipInterleavedOperand().
◆ getMaskTypeFor()
Return the type of the mask type suitable for masking the provided vector type.
This is simply an i1 element type vector of the same (possibly scalable) length.
Definition at line 3448 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), and llvm::MVT::isVector().
◆ getPACKOpcode()
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Definition at line 4709 of file RISCVISelLowering.cpp.
References assert(), llvm_unreachable, and Subtarget.
Referenced by lowerBuildVectorViaPacking().
◆ getPrefTypeAlign()
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Definition at line 29006 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::DataLayout::getPrefTypeAlign(), and llvm::EVT::getTypeForEVT().
◆ getQDOTXResultType()
Definition at line 24490 of file RISCVISelLowering.cpp.
References assert(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf().
Referenced by foldReduceOperandViaVDOT4A().
◆ getRISCVVLOp()
Get a RISC-V target specified VL op for a given SDNode.
Definition at line 8095 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ISD::CTLZ_ZERO_POISON, llvm::ISD::CTTZ_ZERO_POISON, llvm::ISD::FMA, llvm::ISD::FMAXIMUMNUM, llvm::ISD::FMAXNUM, llvm::ISD::FMINIMUMNUM, llvm::ISD::FMINNUM, llvm::ISD::LLRINT, llvm_unreachable, llvm::ISD::LRINT, llvm::ISD::MASKED_SDIV, llvm::ISD::MASKED_SREM, llvm::ISD::MASKED_UDIV, llvm::ISD::MASKED_UREM, OP_CASE, llvm::ISD::OR, ROTR, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, llvm::ISD::STRICT_FMA, VP_CASE, llvm::ISD::VSELECT, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ getRISCVWOpcode()
Definition at line 17091 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::ISD::ROTL, llvm::ISD::ROTR, llvm::ISD::SDIV, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::UDIV, and llvm::ISD::UREM.
◆ getRVPHorizontalMulAccOpcode()
Definition at line 12635 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPHorizontalMulOpcode()
Definition at line 12577 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by lowerRV32HorizontalMul64(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPMulAccHalvesOpcode()
Return the multiply-parts accumulate node for IntNo.
Definition at line 12859 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPMulAddAccOpcode()
Definition at line 12655 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPMulHalvesOpcode()
Return the packed multiply-halves node for a multiply-parts intrinsic.
The scalar spelling maps to the same node; its product is the first element.
Definition at line 12761 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPMulHighAccumulateHalfOpcode()
Return the multiply high accumulate node for IntNo.
Definition at line 12514 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPMulHighAccumulateOpcode()
Definition at line 12493 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPMulHighHalfOpcode()
Return the multiply-high-parts node for a multiply-high-parts intrinsic.
The scalar spelling maps to the same node; its product is the first element.
Definition at line 12533 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPMulHighOpcode()
Definition at line 12437 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPMulPartsAccIntrinsic()
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Return the accumulate form of multiply-parts intrinsic IntNo, or Intrinsic::not_intrinsic if there is none.
Definition at line 12819 of file RISCVISelLowering.cpp.
References llvm::Intrinsic::not_intrinsic.
Referenced by combineAddMulParts().
◆ getRVPNarrowingOpcode()
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Definition at line 12403 of file RISCVISelLowering.cpp.
References llvm_unreachable.
◆ getRVPQFormatAccOpcode()
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Definition at line 12552 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPScalarMulPartsIntrinsic()
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Return the scalar multiply-parts intrinsic computing the first product of packed intrinsic IntNo.
Definition at line 12794 of file RISCVISelLowering.cpp.
References llvm_unreachable.
◆ getRVPScalarOpcode()
Definition at line 12452 of file RISCVISelLowering.cpp.
References llvm::ISD::AVGFLOORS, llvm::ISD::AVGFLOORU, llvm::ISD::AVGSUBFLOORS, llvm::ISD::AVGSUBFLOORU, and llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPShiftOpcode()
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Definition at line 12381 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPWideningMulAccOpcode()
Definition at line 12622 of file RISCVISelLowering.cpp.
References llvm_unreachable.
◆ getRVPWordMulPartsAccOpcodeAndLanes()
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Return {opcode, rs1 lane, rs2 lane} for the word form of accumulate intrinsic IntNo.
Definition at line 12918 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVPWordMulPartsOpcodeAndLanes()
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Return {opcode, rs1 lane, rs2 lane} for the word form of IntNo.
Definition at line 12892 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::ISD::SMUL_LOHI, and llvm::ISD::UMUL_LOHI.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getRVVFPReductionOpAndOperands()
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Definition at line 14568 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstantFP(), llvm::SelectionDAG::getExtractVectorElt(), llvm_unreachable, Subtarget, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMAXIMUM, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMINIMUM, llvm::ISD::VECREDUCE_SEQ_FADD, and Zero.
◆ getRVVReductionOp()
Definition at line 14350 of file RISCVISelLowering.cpp.
References llvm_unreachable, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, and llvm::ISD::VECREDUCE_XOR.
◆ getShlAddShlAdd()
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Definition at line 20965 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_AnyOf(), llvm::SDPatternMatch::m_ConstInt(), llvm::SDPatternMatch::m_ExactSr(), llvm::PatternMatch::m_SpecificInt(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), llvm::ISD::SHL, and X.
Referenced by expandMulToShlAddShlAdd().
◆ getSingleShuffleSrc()
Definition at line 5371 of file RISCVISelLowering.cpp.
References foldConcatVector(), llvm::SDValue::getValueType(), llvm::MVT::getVectorNumElements(), llvm::SDValue::isUndef(), SDValue(), and llvm::V1.
◆ getSmallestVTForIndex()
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Definition at line 11587 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::bitsGT(), DL, llvm::MVT::getDoubleNumVectorElementsVT(), llvm::RISCVTargetLowering::getM1VT(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::isScalableVector(), llvm::MVT::isValid(), and Subtarget.
◆ getTargetNode() [1/4]
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Definition at line 10141 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetBlockAddress(), and N.
◆ getTargetNode() [2/4]
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Definition at line 10147 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetConstantPool(), and N.
◆ getTargetNode() [3/4]
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Definition at line 10136 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetGlobalAddress(), and N.
◆ getTargetNode() [4/4]
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Definition at line 10153 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getTargetJumpTable(), and N.
◆ getVCIXISDNodeVOID()
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Definition at line 14056 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getNode(), Operands, and processVCIXOperands().
◆ getVCIXISDNodeWCHAIN()
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Definition at line 14020 of file RISCVISelLowering.cpp.
References convertFromScalableVector(), DL, llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::SDValue::getValue(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), Operands, processVCIXOperands(), and Subtarget.
◆ getVecReduceOpcode()
Given a binary operator, return the associative generic ISD::VECREDUCE_OP which corresponds to it.
Definition at line 18997 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm_unreachable, Opc, llvm::ISD::OR, llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ISD::UMAX, llvm::ISD::UMIN, llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ISD::VECREDUCE_XOR, and llvm::ISD::XOR.
Referenced by combineBinOpOfExtractToReduceTree().
◆ getVLOperand()
Definition at line 3294 of file RISCVISelLowering.cpp.
References assert(), II, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, and SDValue().
Referenced by lowerVectorIntrinsicScalars().
◆ getVSlidedown()
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Definition at line 4062 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::isUndef(), llvm::RISCVVType::MASK_AGNOSTIC, llvm::Offset, Subtarget, llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED.
Referenced by lowerBUILD_VECTOR(), lowerVECTOR_SHUFFLEAsVSlidedown(), and llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ getVSlideup()
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Definition at line 4074 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::isUndef(), llvm::RISCVVType::MASK_AGNOSTIC, llvm::Offset, Subtarget, llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED.
Referenced by lowerBUILD_VECTOR(), lowerVECTOR_SHUFFLEAsVSlideup(), and llvm::RISCVTargetLowering::PerformDAGCombine().
◆ getWideningInterleave()
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Definition at line 5962 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeTypeToInteger(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getWideningSpread(), llvm::MVT::isFixedLengthVector(), llvm::SDValue::isUndef(), and Subtarget.
◆ getWideningSpread()
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Definition at line 5938 of file RISCVISelLowering.cpp.
References llvm::MVT::changeTypeToInteger(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::ISD::SHL, V, and llvm::ISD::ZERO_EXTEND.
Referenced by getWideningInterleave().
◆ getZeroPaddedAdd()
Given fixed length vectors A and B with equal element types, but possibly different number of elements, return A + B where either A or B is zero padded to the larger number of elements.
Definition at line 24499 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, assert(), B(), DL, llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), and std::swap().
Referenced by foldReduceOperandViaVDOT4A().
◆ hasFPType()
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Definition at line 2855 of file RISCVISelLowering.cpp.
References Subtarget.
Referenced by llvm::RISCVTargetLowering::getFPImmAction().
◆ isCompressMask()
Definition at line 6279 of file RISCVISelLowering.cpp.
References llvm::enumerate(), and llvm::Last.
◆ isElementRotate()
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Definition at line 5487 of file RISCVISelLowering.cpp.
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal().
◆ isI32SignExtended()
Definition at line 25380 of file RISCVISelLowering.cpp.
References llvm::Hi, llvm::isa(), Lo, and llvm::ISD::SRA.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ isInterleaveShuffle()
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Is this shuffle interleaving contiguous elements from one vector into the even elements and contiguous elements from another vector into the odd elements.
EvenSrc will contain the element that should be in the first even element. OddSrc will contain the element that should be in the first odd element. These can be the first element in a source or the element half way through the source.
Definition at line 5430 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::ShuffleVectorInst::isInterleaveMask(), isLegalVTForZvzipInterleavedOperand(), llvm::Size, and Subtarget.
Referenced by llvm::RISCVTargetLowering::isShuffleMaskLegal().
◆ isLegalBitRotate()
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Definition at line 6104 of file RISCVISelLowering.cpp.
References llvm::MVT::getIntegerVT(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ShuffleVectorInst::isBitRotateMask(), and Subtarget.
Referenced by lowerShuffleViaVRegSplitting(), and lowerVECTOR_SHUFFLEAsRotate().
◆ isLegalVTForZvzipDeinterleavedOperand()
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Definition at line 5395 of file RISCVISelLowering.cpp.
References ContainerVT, getContainerForFixedLengthVector(), llvm::RISCVTargetLowering::getLMUL(), llvm::MVT::isFixedLengthVector(), llvm::RISCVVType::LMUL_8, and Subtarget.
◆ isLegalVTForZvzipInterleavedOperand()
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Definition at line 5403 of file RISCVISelLowering.cpp.
References ContainerVT, getContainerForFixedLengthVector(), llvm::MVT::getHalfNumVectorElementsVT(), getLMULOctuple(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::isFixedLengthVector(), and Subtarget.
Referenced by isInterleaveShuffle().
◆ isLocalRepeatingShuffle()
Is this mask local (i.e.
elements only move within their local span), and repeating (that is, the same rearrangement is being done within each span)?
Definition at line 6361 of file RISCVISelLowering.cpp.
References llvm::enumerate(), and I.
◆ isLowSourceShuffle()
Is this mask only using elements from the first span of the input?
Definition at line 6378 of file RISCVISelLowering.cpp.
References llvm::all_of().
◆ isMaskedSlidePair()
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Is this mask representing a masked combination of two slides?
Definition at line 5468 of file RISCVISelLowering.cpp.
References assert(), llvm::isMaskedSlidePair(), and std::swap().
◆ isNonZeroAVL()
Definition at line 14475 of file RISCVISelLowering.cpp.
References llvm::dyn_cast().
Referenced by combineBinOpToReduce(), and lowerReductionSeq().
◆ isPackedZExtShuffleMask()
Definition at line 6606 of file RISCVISelLowering.cpp.
References I.
Referenced by llvm::RISCVTargetLowering::isVectorClearMaskLegal().
◆ isPromotedOpNeedingSplit()
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Definition at line 8212 of file RISCVISelLowering.cpp.
References llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), llvm::is_contained(), llvm::MVT::isVector(), Subtarget, TLI, and ZvfbfaOps.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ isSimm12Constant()
Definition at line 10447 of file RISCVISelLowering.cpp.
References llvm::isa(), and V.
Referenced by lowerSelectToBinOp().
◆ isSimpleVIDSequence()
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Definition at line 4124 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::enumerate(), getExactInteger(), llvm::APInt::getSExtValue(), isConstant(), llvm::APInt::sdiv(), and llvm::APInt::srem().
Referenced by lowerBuildVectorViaVID(), and llvm::RISCVTargetLowering::PerformDAGCombine().
◆ isSpanSplatShuffle()
Return true for a mask which performs an arbitrary shuffle within the first span, and then repeats that same result across all remaining spans.
Note that this doesn't check if all the inputs come from a single span!
Definition at line 6385 of file RISCVISelLowering.cpp.
References llvm::enumerate(), and I.
◆ isValidEGW()
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Definition at line 12374 of file RISCVISelLowering.cpp.
References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::RISCV::RVVBitsPerBlock, and Subtarget.
◆ isVLMax()
Definition at line 23526 of file RISCVISelLowering.cpp.
References llvm::cast(), getReg(), llvm::isa(), and llvm::isAllOnesConstant().
Referenced by combineTruncOfSraSext(), and performVSlideUpDownCombine().
◆ legalizeScatterGatherIndexType()
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Definition at line 25009 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsLT(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getSubtarget(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorVT(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::UNSIGNED_SCALED.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ lookupMaskedIntrinsic()
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Definition at line 28182 of file RISCVISelLowering.cpp.
References assert(), llvm::RISCVVInversePseudosTable::getBaseInfo(), and llvm::Masked.
Referenced by emitVFROUND_NOEXCEPT_MASK().
◆ LowerATOMIC_FENCE()
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Definition at line 7816 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::ISD::MEMBARRIER, llvm::SequentiallyConsistent, llvm::SyncScope::SingleThread, Subtarget, and llvm::SyncScope::System.
◆ lowerBitreverseShuffle()
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Definition at line 6054 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ShuffleVectorInst::isReverseMask(), llvm::SDValue::isUndef(), llvm::PowerOf2Ceil(), SDValue(), llvm::ArrayRef< T >::size(), llvm::ISD::SRL, Subtarget, uint64_t, and V.
◆ lowerBUILD_VECTOR()
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Definition at line 4786 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::all_of(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, llvm::ArrayRef(), assert(), llvm::ISD::BUILD_VECTOR, C(), llvm::cast(), llvm::MVT::changeVectorElementType(), llvm::ISD::CONCAT_VECTORS, ContainerVT, convertFromScalableVector(), convertToScalableVector(), llvm::count_if(), DL, llvm::dyn_cast(), llvm::enumerate(), llvm::SelectionDAG::getAnyExtOrTrunc(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::MVT::getFixedSizeInBits(), llvm::SelectionDAG::getInsertSubvector(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getM1VT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::getSplatValue(), llvm::SelectionDAG::getSplatVector(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), getVSlidedown(), getVSlideup(), llvm::Hi, I, llvm::ISD::isBuildVectorOfConstantFPSDNodes(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm_unreachable, llvm::RISCVVType::LMUL_2, llvm::RISCVVType::LMUL_4, llvm::RISCVVType::LMUL_8, Lo, lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), llvm::PatternMatch::m_ExtractElt(), llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_Zero(), llvm::RISCVVType::MASK_AGNOSTIC, matchSplatAsGather(), llvm::Offset, Opc, Operands, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), llvm::ISD::SCALAR_TO_VECTOR, SDValue(), llvm::ISD::SETNE, llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Splat, Subtarget, llvm::RISCVVType::TAIL_AGNOSTIC, V, and llvm::ISD::VSELECT.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerBuildVectorOfConstants()
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Definition at line 4469 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), llvm::cast(), llvm::MVT::changeVectorElementType(), llvm::SelectionDAG::ComputeMaxSignificantBits(), ContainerVT, convertFromScalableVector(), convertToScalableVector(), llvm::divideCeil(), DL, llvm::enumerate(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertVectorElt(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::MVT::getSizeInBits(), llvm::getSplatValue(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), I, llvm::ISD::isBuildVectorAllOnes(), llvm::ISD::isBuildVectorAllZeros(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isInt(), llvm::MVT::isInteger(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaVID(), llvm::maskTrailingOnes(), Opc, SDValue(), llvm::SelectionDAG::shouldOptForSize(), llvm::SignExtend64(), llvm::Splat, Subtarget, uint64_t, and V.
Referenced by lowerBUILD_VECTOR().
◆ lowerBuildVectorViaDominantValues()
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Try and optimize BUILD_VECTORs with "dominant values" - these are values which constitute a large proportion of the elements.
In such cases we can splat a vector with the dominant element and make up the shortfall with INSERT_VECTOR_ELTs. Returns SDValue if not profitable. Note that this includes vectors of 2 elements by association. The upper-most element is the "dominant" one, allowing us to use a splat to "insert" the upper element, and an insert of the lower element at position 0, which improves codegen.
Definition at line 4364 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::changeVectorElementType(), ContainerVT, convertFromScalableVector(), convertToScalableVector(), llvm::Count, llvm::count_if(), DL, llvm::dyn_cast(), llvm::enumerate(), llvm::SelectionDAG::getBuildVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getInsertVectorElt(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getUNDEF(), llvm::detail::DenseSetImpl< ValueT, MapTy >::insert(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::Log2_32(), SDValue(), llvm::SelectionDAG::shouldOptForSize(), llvm::DenseMapBase< StorageT, KeyT, ValueT, KeyInfoT, BucketT >::size(), Subtarget, llvm::transform(), V, llvm::V1, and llvm::ISD::VSELECT.
Referenced by lowerBUILD_VECTOR(), and lowerBuildVectorOfConstants().
◆ lowerBuildVectorViaPacking()
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Double the element size of the build vector to reduce the number of vslide1down in the build vector chain.
In the worst case, this trades three scalar operations for 1 vector operation. Scalar operations are generally lower latency, and for out-of-order cores we also benefit from additional parallelism.
Definition at line 4729 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::AND, assert(), B(), llvm::ISD::BITCAST, llvm::SDNodeFlags::Disjoint, DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), getPACKOpcode(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isInteger(), llvm::ISD::OR, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::reserve(), SDValue(), llvm::ISD::SHL, llvm::SmallVectorTemplateCommon< T, typename >::size(), and Subtarget.
Referenced by lowerBUILD_VECTOR().
◆ lowerBuildVectorViaVID()
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Definition at line 4285 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::MVT::changeVectorElementTypeToInteger(), ContainerVT, convertFromScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSignedConstant(), INT64_MIN, llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isInt(), llvm::isPowerOf2_32(), llvm::isPowerOf2_64(), isSimpleVIDSequence(), llvm::isUInt(), llvm::Log2_64(), llvm::ISD::MUL, SDValue(), llvm::ISD::SHL, llvm::ISD::SINT_TO_FP, llvm::ISD::SRL, llvm::ISD::SUB, and Subtarget.
Referenced by lowerBuildVectorOfConstants(), and llvm::RISCVTargetLowering::LowerOperation().
◆ lowerConstant()
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Definition at line 7735 of file RISCVISelLowering.cpp.
References assert(), llvm::cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::RISCVMatInt::generateTwoRegInstSeq(), Imm, llvm::isInt(), SDValue(), llvm::SelectionDAG::shouldOptForSize(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and Subtarget.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerCONVERT_FROM_ARBITRARY_FP()
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Definition at line 12276 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::ISD::CONVERT_FROM_ARBITRARY_FP, convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getPOISON(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::MVT::isFixedLengthVector(), llvm::EVT::isSimple(), llvm::APFloatBase::S_Float8E5M2, SDValue(), Subtarget, and uint64_t.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerCttzElts()
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Definition at line 12253 of file RISCVISelLowering.cpp.
References ContainerVT, convertToScalableVector(), llvm::ISD::CTTZ_ELTS_ZERO_POISON, DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getElementCount(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::isFixedLengthVector(), llvm::ISD::SETLT, and Subtarget.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerDisjointIndicesShuffle()
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Given a shuffle where the indices are disjoint between the two sources, e.g.:
t2:v4i8 = vector_shuffle t0:v4i8, t1:v4i8, <2, 7, 1, 4>
Merge the two sources into one and do a single source shuffle:
t2:v4i8 = vselect t1:v4i8, t0:v4i8, <0, 1, 0, 1> t3:v4i8 = vector_shuffle t2:v4i8, undef, <2, 3, 1, 0>
A vselect will either be merged into a masked instruction or be lowered as a vmerge.vvm, which is cheaper than a vrgather.vv.
Definition at line 6310 of file RISCVISelLowering.cpp.
References llvm::MVT::changeVectorElementType(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), I, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), Select, Subtarget, and llvm::ISD::VSELECT.
◆ lowerFABSorFNEG()
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Definition at line 8011 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, assert(), DL, llvm::ISD::FABS, llvm::ISD::FNEG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignMask(), Subtarget, and llvm::ISD::XOR.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFCOPYSIGN()
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Definition at line 8034 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::ISD::BITCAST, llvm::SDNodeFlags::Disjoint, DL, llvm::ISD::FCOPYSIGN, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::APInt::getSignedMaxValue(), llvm::APInt::getSignMask(), getValue(), llvm::SDValue::getValueSizeInBits(), llvm_unreachable, llvm::ISD::OR, llvm::ISD::SHL, Sign, llvm::ISD::SRL, and Subtarget.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFixedVectorSegLoadIntrinsics()
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Definition at line 14066 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::cast(), ContainerVT, convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::MVT::getRISCVVectorTupleVT(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm_unreachable, llvm::Load, llvm::Log2_64(), llvm::RISCVVType::MASK_AGNOSTIC, Results, Subtarget, and llvm::RISCVVType::TAIL_AGNOSTIC.
◆ lowerFixedVectorSegStoreIntrinsics()
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Definition at line 14211 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::cast(), ContainerVT, convertToScalableVector(), DL, getContainerForFixedLengthVector(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::MVT::getRISCVVectorTupleVT(), llvm::MVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_VOID, llvm_unreachable, llvm::Log2_64(), and Subtarget.
◆ lowerFMAXIMUM_FMINIMUM()
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Definition at line 7936 of file RISCVISelLowering.cpp.
References ContainerVT, convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::FMAXIMUM, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::isFixedLengthVector(), llvm::SelectionDAG::isKnownNeverNaN(), llvm::MVT::isVector(), Opc, llvm::ISD::SETOEQ, Subtarget, X, and Y.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFP_TO_INT()
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Definition at line 3739 of file RISCVISelLowering.cpp.
References DL, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::ISD::STRICT_FP_EXTEND, and Subtarget.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFP_TO_INT_SAT()
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Definition at line 3626 of file RISCVISelLowering.cpp.
References assert(), llvm::cast(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), Opc, llvm::RISCVFPRndMode::RTZ, SDValue(), llvm::ISD::SETUO, and Subtarget.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerFTRUNC_FCEIL_FFLOOR_FROUND()
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Definition at line 3993 of file RISCVISelLowering.cpp.
References llvm::APFloat::convertFromAPInt(), DL, llvm::SelectionDAG::getConstantFP(), llvm::MVT::getFltSemantics(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::isVector(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, SDValue(), llvm::APFloatBase::semanticsPrecision(), llvm::SelectionDAG::shouldOptForSize(), and Subtarget.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerGetVectorLength()
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Definition at line 12218 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::RISCVVType::encodeLMUL(), llvm::RISCVVType::encodeSEW(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isPowerOf2_32(), N, llvm::RISCV::RVVBitsPerBlock, Subtarget, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ lowerINT_TO_FP()
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Definition at line 3599 of file RISCVISelLowering.cpp.
References DL, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::ISD::STRICT_FP_ROUND, and Subtarget.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ LowerPREFETCH()
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Definition at line 7805 of file RISCVISelLowering.cpp.
References Subtarget.
◆ lowerPZExt()
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Definition at line 12424 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ISD::SPLAT_VECTOR, Subtarget, and Zero.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ lowerReductionSeq()
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Helper to lower a reduction sequence of the form: scalar = reduce_op vec, scalar_start.
Definition at line 14484 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MVT::bitsLE(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtractVectorElt(), llvm::SelectionDAG::getInsertSubvector(), llvm::RISCVTargetLowering::getM1VT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), isNonZeroAVL(), lowerScalarInsert(), Subtarget, and llvm::RISCVVType::TAIL_AGNOSTIC.
◆ lowerRV32HorizontalMul64()
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Definition at line 12685 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtractVectorElt(), llvm::SelectionDAG::getNode(), getRVPHorizontalMulOpcode(), llvm::SDValue::getSimpleValueType(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm_unreachable, Opc, llvm::ISD::SMUL_LOHI, llvm::SelectionDAG::SplitVector(), std::swap(), llvm::ISD::UMUL_LOHI, V, and Zero.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ lowerScalarInsert()
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Definition at line 5294 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLE(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::MVT::getVectorElementType(), llvm::isa(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::MVT::isScalableVector(), lowerScalarSplat(), llvm::ISD::SIGN_EXTEND, and Subtarget.
Referenced by combineBinOpToReduce(), llvm::RISCVTargetLowering::LowerOperation(), and lowerReductionSeq().
◆ lowerScalarSplat()
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Definition at line 5240 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::MVT::changeVectorElementType(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::isa(), llvm::MVT::isFloatingPoint(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::SDValue::isUndef(), lowerScalarSplat(), llvm::ISD::SIGN_EXTEND, llvm::Splat, splatSplitI64WithVL(), and Subtarget.
Referenced by lowerScalarInsert(), lowerScalarSplat(), and llvm::RISCVTargetLowering::PerformDAGCombine().
◆ lowerSelectToBinOp()
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Definition at line 10451 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, CC, DL, llvm::dyn_cast(), llvm::SelectionDAG::getAllOnesConstant(), llvm::SDNode::getAsAPIntVal(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getOperandCondCode(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::SelectionDAG::getSignedTargetConstant(), llvm::SelectionDAG::getTargetConstant(), INT64_MIN, llvm::isa(), llvm::isAllOnesConstant(), llvm::isInt(), llvm::isNullConstant(), llvm::isPowerOf2_64(), llvm::MVT::isScalarInteger(), isSimm12Constant(), LHS, llvm::Log2_64(), matchSetCC(), N, llvm::ISD::OR, RHS, SDValue(), llvm::ISD::SETCC, llvm::ISD::SHL, Subtarget, uint64_t, and llvm::ISD::XOR.
◆ lowerShuffleViaVRegSplitting()
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Definition at line 6151 of file RISCVISelLowering.cpp.
References assert(), ContainerVT, convertToScalableVector(), llvm::Data, DL, getContainerForFixedLengthVector(), llvm::MVT::getFixedSizeInBits(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), llvm::RISCVTargetLowering::getM1VT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::getVectorVT(), isLegalBitRotate(), N, Operands, llvm::processShuffleMasks(), SDValue(), Subtarget, and llvm::V1.
◆ lowerVECTOR_SHUFFLEAsPPair()
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Definition at line 6656 of file RISCVISelLowering.cpp.
References DL, llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), I, llvm::SelectionDAG::isSplatValue(), Local, Opc, P, SDValue(), and llvm::V1.
◆ lowerVECTOR_SHUFFLEAsPSlide1()
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Definition at line 6497 of file RISCVISelLowering.cpp.
References llvm::all_of(), assert(), llvm::ArrayRef< T >::back(), llvm::ISD::CONCAT_VECTORS, DL, llvm::ArrayRef< T >::drop_back(), llvm::ArrayRef< T >::drop_front(), llvm::enumerate(), llvm::ISD::FSHL, llvm::ISD::FSHR, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtractVectorElt(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarSizeInBits(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::Hi, Lo, SDValue(), llvm::ISD::SHL, llvm::SelectionDAG::SplitVector(), llvm::ISD::SRL, Subtarget, and llvm::V1.
◆ lowerVECTOR_SHUFFLEAsPUnzip()
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Definition at line 6475 of file RISCVISelLowering.cpp.
References DL, llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::ShuffleVectorInst::isDeInterleaveMaskOfFactor(), Opc, SDValue(), and llvm::V1.
◆ lowerVECTOR_SHUFFLEAsPZip()
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Definition at line 6433 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getExtractSubvector(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getVectorNumElements(), llvm::ShuffleVectorInst::isInterleaveMask(), llvm::SDValue::isUndef(), SDValue(), Subtarget, and llvm::V1.
◆ lowerVECTOR_SHUFFLEAsRotate()
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Definition at line 6123 of file RISCVISelLowering.cpp.
References llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::MVT::getScalarType(), llvm::SDNode::getValueType(), isLegalBitRotate(), llvm::ISD::ROTL, SDValue(), and Subtarget.
◆ lowerVECTOR_SHUFFLEAsRV32PNarrowingShift()
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Definition at line 6620 of file RISCVISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, foldConcatVector(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::ShuffleVectorInst::isDeInterleaveMaskOfFactor(), SDValue(), Subtarget, and llvm::V1.
◆ lowerVECTOR_SHUFFLEAsVRGatherVX()
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Match a single source shuffle which is an identity except that some particular element is repeated.
This can be lowered as a masked vrgather.vi/vx. Note that the two source form of this is handled by the recursive splitting logic and doesn't need special handling.
Definition at line 5524 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::enumerate(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SDNode::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), I, llvm::SDValue::isUndef(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Splat, Subtarget, llvm::V1, and llvm::ISD::VSELECT.
◆ lowerVECTOR_SHUFFLEAsVSlide1()
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Match v(f)slide1up/down idioms.
These operations involve sliding N-1 elements to make room for an inserted scalar at one end.
Definition at line 5743 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::sampleprof::Base, llvm::cast(), ContainerVT, convertFromScalableVector(), convertToScalableVector(), DL, E(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::isa(), llvm::MVT::isFloatingPoint(), llvm::Offset, SDValue(), llvm::Splat, Subtarget, std::swap(), and llvm::V1.
◆ lowerVECTOR_SHUFFLEAsVSlidedown()
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Definition at line 5573 of file RISCVISelLowering.cpp.
References ContainerVT, convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getUNDEF(), getVSlidedown(), llvm::Offset, SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), Subtarget, uint64_t, and llvm::V1.
◆ lowerVECTOR_SHUFFLEAsVSlideup()
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Definition at line 5648 of file RISCVISelLowering.cpp.
References ContainerVT, convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getConstant(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorNumElements(), getVSlideup(), llvm::ShuffleVectorInst::isInsertSubvectorMask(), llvm::RISCVVType::MASK_AGNOSTIC, SDValue(), Subtarget, llvm::RISCVVType::TAIL_AGNOSTIC, llvm::RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED, and llvm::V1.
◆ lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND()
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Definition at line 3801 of file RISCVISelLowering.cpp.
References assert(), ContainerVT, llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FNEARBYINT, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorVT(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SETOLT, and Subtarget.
Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND().
◆ lowerVectorIntrinsicScalars()
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Definition at line 12037 of file RISCVISelLowering.cpp.
References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::RISCVTargetLowering::computeVLMAXBounds(), DL, llvm::RISCVVType::encodeSEW(), getAllOnesMask(), llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorVT(), getVLOperand(), II, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::MVT::isScalarInteger(), llvm::SDValue::isUndef(), Operands, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, splatSplitI64WithVL(), llvm::SelectionDAG::SplitScalar(), Subtarget, llvm::RISCVVType::TAIL_AGNOSTIC, llvm::ISD::TRUNCATE, and uint64_t.
◆ lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND()
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Definition at line 3892 of file RISCVISelLowering.cpp.
References assert(), ContainerVT, llvm::APFloat::convertFromAPInt(), convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstantFP(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::RISCVFPRndMode::Invalid, llvm::MVT::isFixedLengthVector(), llvm_unreachable, matchRoundingOp(), llvm::APFloatBase::rmNearestTiesToEven, llvm::APFloatBase::semanticsPrecision(), llvm::ISD::SETOLT, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FNEARBYINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, llvm::ISD::STRICT_FTRUNC, and Subtarget.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerVectorXRINT_XROUND()
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Definition at line 4021 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), convertFromScalableVector(), convertToScalableVector(), DL, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::getVectorElementType(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isVector(), matchRoundingOp(), and Subtarget.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ lowerZvzipVPAIR()
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Definition at line 5844 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), ContainerVT, convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::isFixedLengthVector(), Opc, and Subtarget.
◆ lowerZvzipVUNZIP()
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Definition at line 5900 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), ContainerVT, convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::isFixedLengthVector(), Opc, and Subtarget.
◆ lowerZvzipVZIP()
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Definition at line 5873 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementTypeToInteger(), ContainerVT, convertFromScalableVector(), convertToScalableVector(), DL, llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::MVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::isFixedLengthVector(), and Subtarget.
◆ matchIndexAsShuffle()
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Match the index vector of a scatter or gather node as the shuffle mask which performs the rearrangement if possible.
Will only match if all lanes are touched, and thus replacing the scatter or gather with a unit strided access and shuffle is legal.
Definition at line 25044 of file RISCVISelLowering.cpp.
References llvm::BitVector::all(), assert(), C(), llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), llvm::BitVector::set(), and uint64_t.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ matchIndexAsWiderOp()
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Match the index of a gather or scatter operation as an operation with twice the element width and half the number of elements.
This is generally profitable (if legal) because these operations are linear in VL, so even if we cause some extract VTYPE/VL toggles, we still come out ahead.
Definition at line 25079 of file RISCVISelLowering.cpp.
References C(), llvm::EVT::getScalarStoreSize(), llvm::EVT::getVectorNumElements(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVectorAllOnes(), llvm::Last, and uint64_t.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ matchRoundingOp()
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Definition at line 3764 of file RISCVISelLowering.cpp.
References llvm::RISCVFPRndMode::DYN, llvm::ISD::FCEIL, llvm::ISD::FFLOOR, llvm::ISD::FRINT, llvm::ISD::FROUND, llvm::ISD::FROUNDEVEN, llvm::ISD::FTRUNC, llvm::RISCVFPRndMode::Invalid, llvm::ISD::LLRINT, llvm::ISD::LLROUND, llvm::ISD::LRINT, llvm::ISD::LROUND, Opc, llvm::RISCVFPRndMode::RDN, llvm::RISCVFPRndMode::RMM, llvm::RISCVFPRndMode::RNE, llvm::RISCVFPRndMode::RTZ, llvm::RISCVFPRndMode::RUP, llvm::ISD::STRICT_FCEIL, llvm::ISD::STRICT_FFLOOR, llvm::ISD::STRICT_FRINT, llvm::ISD::STRICT_FROUND, llvm::ISD::STRICT_FROUNDEVEN, llvm::ISD::STRICT_FTRUNC, llvm::ISD::STRICT_LLRINT, llvm::ISD::STRICT_LLROUND, llvm::ISD::STRICT_LRINT, and llvm::ISD::STRICT_LROUND.
Referenced by lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT_XROUND(), performFP_TO_INT_SATCombine(), and performFP_TO_INTCombine().
◆ matchSelectAddSub()
Definition at line 24285 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, B(), llvm::ISD::SUB, and std::swap().
Referenced by performVECTOR_SHUFFLECombine(), and performVSELECTCombine().
◆ matchSetCC()
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Definition at line 10424 of file RISCVISelLowering.cpp.
References assert(), CC, llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getOperandCondCode(), llvm::ISD::getSetCCInverse(), llvm::ISD::getSetCCSwappedOperands(), llvm::SDValue::getValueType(), LHS, RHS, and llvm::ISD::SETCC.
◆ matchSplatAsGather()
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Definition at line 4230 of file RISCVISelLowering.cpp.
References ContainerVT, convertFromScalableVector(), convertToScalableVector(), DL, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getInsertSubvector(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorMinNumElements(), llvm::MVT::isFixedLengthVector(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE(), llvm::TargetLoweringBase::isTypeLegal(), SDValue(), and Subtarget.
Referenced by lowerBUILD_VECTOR(), and llvm::RISCVTargetLowering::PerformDAGCombine().
◆ narrowIndex()
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According to the property that indexed load/store instructions zero-extend their indices, try to narrow the type of index operand.
Definition at line 21291 of file RISCVISelLowering.cpp.
References llvm::EVT::bitsLT(), C(), llvm::EVT::changeVectorElementType(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMinLeadingZeros(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getRoundIntegerType(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::APInt::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::ISD::isConstantSplatVector(), llvm::Known, N, llvm::SDNode::ops(), llvm::PowerOf2Ceil(), llvm::ISD::SHL, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ negateFMAOpcode()
Definition at line 23650 of file RISCVISelLowering.cpp.
References llvm_unreachable.
Referenced by combineFMA(), combineFMADDSUB(), combineVFMADD_VLWithVFNEG_VL(), and llvm::X86TargetLowering::getNegatedExpression().
◆ performADDCombine()
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Definition at line 20002 of file RISCVISelLowering.cpp.
References combineAddMulh(), combineAddMulParts(), combineAddOfBooleanXor(), combineAddOfExts(), combineAddOfExtsAlreadyExtended(), combineAddPackedByteDot(), combineBinOpOfExt(), combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combinePExtWideningAddAcc(), combinePExtWideningAddSub(), combineSelectAndUseCommutative(), combineShlAddIAdd(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), N, Subtarget, transformAddImmMulImm(), transformAddShlImm(), and V.
◆ performANDCombine()
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Definition at line 20570 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineNarrowableShiftedLoad(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isOneConstant(), N, reduceANDOfAtomicLoad(), reverseZExtICmpCombine(), llvm::ISD::SRL, Subtarget, llvm::ISD::TRUNCATE, V, and llvm::ISD::ZERO_EXTEND.
◆ performBITREVERSECombine()
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Definition at line 23228 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BSWAP, DL, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::has_single_bit(), llvm::EVT::isScalarInteger(), N, SDValue(), and Subtarget.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performBUILD_VECTORCombine()
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If we have a build_vector where each lane is binop X, C, where C is a constant (but not necessarily the same constant on all lanes), form binop (build_vector x1, x2, ...), (build_vector c1, c2, c3, ..).
We assume that materializing a constant build vector will be no more expensive that performing O(n) binops.
Definition at line 24432 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::isa(), llvm::SelectionDAG::isSafeToSpeculativelyExecute(), llvm::EVT::isScalableVector(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), Subtarget, and TLI.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performCONCAT_VECTORSCombine()
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Definition at line 24691 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::cast(), llvm::MVT::changeVectorElementType(), DL, llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::end(), llvm::BaseIndexOffset::equalBaseIndex(), llvm::LoadSDNode::getBasePtr(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNegative(), llvm::getOffset(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::EVT::getSimpleVT(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getSplat(), llvm::SelectionDAG::getStridedLoadVP(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ISD::isNormalLoad(), llvm::EVT::isScalableVector(), llvm::SelectionDAG::makeEquivalentMemoryOrdering(), llvm::BaseIndexOffset::match(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), Subtarget, TLI, uint64_t, and llvm::MemoryLocation::UnknownSize.
◆ performFP_TO_INT_SATCombine()
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Definition at line 23165 of file RISCVISelLowering.cpp.
References llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelectCC(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getZeroExtendInReg(), llvm::RISCVFPRndMode::Invalid, matchRoundingOp(), N, Opc, SDValue(), llvm::ISD::SETUO, Subtarget, and TLI.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performFP_TO_INTCombine()
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Definition at line 23060 of file RISCVISelLowering.cpp.
References ContainerVT, convertFromScalableVector(), convertToScalableVector(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::RISCVFPRndMode::DYN, llvm::ISD::FP_TO_SINT, getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::RISCVFPRndMode::Invalid, llvm::EVT::isFixedLengthVector(), llvm::MVT::isFixedLengthVector(), llvm::EVT::isVector(), matchRoundingOp(), N, Opc, llvm::RISCVFPRndMode::RTZ, SDValue(), Subtarget, TLI, and llvm::ISD::TRUNCATE.
◆ performINSERT_VECTOR_ELTCombine()
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Definition at line 24617 of file RISCVISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::dyn_cast(), llvm::SelectionDAG::getInsertVectorElt(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), llvm::ISD::INSERT_VECTOR_ELT, llvm::isa(), llvm::ISD::isBuildVectorOfConstantSDNodes(), llvm::EVT::isScalableVector(), LHS, N, llvm::SDNode::ops(), RHS, SDValue(), Subtarget, and TLI.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performMaskedLoadToVPLoadCombine()
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Given.
we can turn this use a vp.load + vp.merge instead to avoid emitting mask. The VL of these two vp operations would be min(m, <number of vector elements>)
Definition at line 23434 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, llvm::cast(), CC, DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoadVP(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SelectionDAG::getSplatValue(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::isFixedLengthVector(), llvm::EVT::isInteger(), llvm::ISD::isSignedIntSetCC(), llvm::EVT::isVector(), llvm::SDPatternMatch::m_SetCC(), llvm::PatternMatch::m_Value(), llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SETLT, llvm::ISD::SETULT, llvm::ISD::SMIN, and llvm::ISD::UMIN.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performMemPairCombine()
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Definition at line 22975 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, C1, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), getExtensionType(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemoryVT(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::MachineFunction::getSubtarget(), llvm::Use::getUser(), llvm::LSBaseSDNode::isIndexed(), llvm::isShiftedUInt(), llvm::MemSDNode::isSimple(), llvm::ISD::LOAD, N, SDValue(), Subtarget, tryMemPairCombine(), and llvm::SDNode::uses().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performMULCombine()
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Definition at line 21237 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, combineBinOpOfExt(), combinePExtWideningMul(), combineVectorMulToSraBitcast(), DL, expandMul(), llvm::SelectionDAG::getNode(), llvm::isOneOrOneSplat(), llvm::EVT::isVector(), llvm::ISD::MUL, N, SDValue(), llvm::ISD::SUB, Subtarget, std::swap(), and V.
◆ performORCombine()
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Definition at line 20789 of file RISCVISelLowering.cpp.
References combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineDeMorganOfBoolean(), combineOrAndToBitfieldInsert(), combineOrOfCZERO(), combineOrToBitfieldInsert(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), N, Subtarget, and V.
◆ performP_BITCASTCombine()
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Definition at line 23347 of file RISCVISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::EVT::getSizeInBits(), llvm::APInt::getSplat(), llvm::SDValue::getValueType(), llvm::ISD::isConstantSplatVector(), N, SDValue(), and Subtarget.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performReverseEVLCombine()
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Definition at line 23256 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::append_range(), llvm::sampleprof::Base, llvm::LocationSize::beforeOrAfterPointer(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::dyn_cast(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::MemSDNode::getAddressSpace(), llvm::MemSDNode::getAlign(), llvm::VPLoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::VPLoadSDNode::getMask(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getStridedLoadVP(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::VPLoadSDNode::getVectorLength(), llvm::TargetLoweringBase::isBinOp(), llvm::EVT::isByteSized(), llvm::VPLoadSDNode::isExpandingLoad(), llvm::isOneOrOneSplat(), llvm::SelectionDAG::isSplatValue(), m_ReverseEVL, llvm::PatternMatch::m_Specific(), llvm::PatternMatch::m_Value(), llvm::ISD::MUL, N, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SUB, Subtarget, uint64_t, and X.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performSELECTCombine()
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Definition at line 24406 of file RISCVISelLowering.cpp.
References Folded, foldSelectOfCTTZOrCTLZ(), foldSelectToUSATI(), N, SDValue(), Subtarget, tryFoldSelectIntoOp(), useInversedSetcc(), and V.
◆ performSETCCCombine()
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Definition at line 21586 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::bit_width(), C1, canonicalizeMaskForVLPredicate(), llvm::cast(), combineVectorSizedSetCCEquality(), llvm::SelectionDAG::ComputeMaxSignificantBits(), Cond, llvm::countr_one(), llvm::APInt::countr_zero(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getBoolConstant(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::APInt::getOneBitSet(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::APInt::getSExtValue(), llvm::SelectionDAG::getSignedConstant(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getValueType(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isInt(), llvm::isMask_64(), llvm::APInt::isNegatedPowerOf2(), llvm::isNullConstant(), llvm::isPowerOf2_32(), llvm::isUInt(), llvm::SelectionDAG::MaskedValueIsZero(), N, SDValue(), llvm::ISD::SETNE, llvm::ISD::SIGN_EXTEND_INREG, llvm::SignExtend64(), llvm::ISD::SRA, llvm::ISD::SRL, Subtarget, uint64_t, and V.
◆ performSHLCombine()
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Definition at line 25249 of file RISCVISelLowering.cpp.
References combineOp_VLToVWOp_VL(), llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), getDefaultScalableVLOps(), llvm::SelectionDAG::getNode(), llvm::MVT::getScalarSizeInBits(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getUNDEF(), llvm::APInt::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::ISD::isConstantSplatVector(), LHS, llvm_unreachable, N, RHS, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND, Subtarget, uint64_t, V, and llvm::ISD::ZERO_EXTEND.
◆ performSIGN_EXTEND_INREGCombine()
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Definition at line 21693 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::EVT::bitsGE(), llvm::cast(), llvm::SelectionDAG::computeKnownBits(), llvm::KnownBits::countMaxActiveBits(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getFreeze(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::MVT::getVT(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::isAllOnesConstant(), llvm::EVT::isFixedLengthVector(), N, Opc, SDValue(), llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, Subtarget, and llvm::ISD::XOR.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performSRACombine()
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Definition at line 23795 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::cast(), llvm::countr_zero(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isa(), N, SDValue(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::Size, llvm::ISD::SRA, llvm::ISD::SUB, Subtarget, uint64_t, and llvm::SDNode::users().
◆ performSRLCombine()
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Definition at line 23768 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::CLMULR, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_Clmul(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_SpecificInt(), llvm::SDPatternMatch::m_Srl(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SHL, llvm::ISD::SRL, Subtarget, X, and Y.
◆ performSUBCombine()
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Definition at line 20163 of file RISCVISelLowering.cpp.
References combineBinOpOfExt(), combineNegOfSelectCCSubs(), combinePExtWideningAddSub(), combinePExtWideningSubAcc(), combineSelectAndUse(), combineSubOfBoolean(), combineSubShiftToOrcB(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getOperandCondCode(), llvm::SelectionDAG::getShiftAmountConstant(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isNullConstant(), llvm::isPowerOf2_64(), llvm::Log2_64(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_OneUse(), llvm::SDPatternMatch::m_Srl(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SHL, llvm::ISD::SRA, Subtarget, uint64_t, V, and X.
◆ performTRUNCATECombine()
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Definition at line 20399 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, combinePExtTruncate(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isa(), llvm::EVT::isFixedLengthVector(), N, SDValue(), llvm::ISD::SRL, Subtarget, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVECREDUCECombine()
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Definition at line 24603 of file RISCVISelLowering.cpp.
References DL, foldReduceOperandViaVDOT4A(), llvm::SelectionDAG::getNode(), N, SDValue(), Subtarget, TLI, V, and llvm::ISD::VECREDUCE_ADD.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVECTOR_INTERLEAVECombine()
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Definition at line 23480 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::EVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getExtractSubvector(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::MVT::getVectorMinNumElements(), llvm::SelectionDAG::getVTList(), I, N, Operands, SDValue(), std::swap(), V, and llvm::ISD::VECTOR_INTERLEAVE.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVECTOR_SHUFFLECombine()
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Definition at line 24818 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, assert(), B(), C(), llvm::cast(), CC, compressShuffleOfShuffles(), DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLogicalNOT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::EVT::isFloatingPoint(), llvm::isPowerOf2_64(), llvm::ShuffleVectorInst::isSelectMask(), matchSelectAddSub(), N, llvm::narrowShuffleMaskElts(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), SDValue(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::Sub, Subtarget, TLI, V, llvm::V1, and llvm::ISD::VSELECT.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVEXT_VLCombine()
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Definition at line 23742 of file RISCVISelLowering.cpp.
References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDPatternMatch::m_Node(), llvm::MIPatternMatch::m_OneUse(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), and Subtarget.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVFMADD_VLCombine()
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Definition at line 23727 of file RISCVISelLowering.cpp.
References combineOp_VLToVWOp_VL(), combineVFMADD_VLWithVFNEG_VL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getSelectionDAGInfo(), llvm::SelectionDAGTargetInfo::isTargetStrictFPOpcode(), N, SDValue(), Subtarget, and V.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVP_STORECombine()
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Definition at line 23363 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::sampleprof::Base, llvm::LocationSize::beforeOrAfterPointer(), llvm::cast(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getStridedStoreVP(), llvm::EVT::getVectorElementType(), llvm::EVT::isByteSized(), llvm::isOneOrOneSplat(), llvm::MIPatternMatch::m_OneUse(), m_ReverseEVL, llvm::PatternMatch::m_Specific(), llvm::PatternMatch::m_Value(), llvm::ISD::MUL, N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SUB, Subtarget, and uint64_t.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVSELECTCombine()
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Definition at line 24305 of file RISCVISelLowering.cpp.
References A(), llvm::ISD::ADD, B(), canonicalizeVSelectTrueToOneUse(), CC, DL, llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::getNegative(), llvm::SelectionDAG::getNode(), matchSelectAddSub(), N, SDValue(), llvm::Sub, Subtarget, V, and llvm::ISD::VSELECT.
◆ performVSlideUpDownCombine()
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Definition at line 23532 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::KnownBits::add(), assert(), llvm::SelectionDAG::computeKnownBits(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getPOISON(), llvm::SDValue::isUndef(), isVLMax(), N, SDValue(), Subtarget, and llvm::KnownBits::uge().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVWABDACombine()
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Definition at line 22771 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getVectorElementType(), llvm::SDNode::isUndef(), N, SDValue(), and Subtarget.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVWABDACombineWV()
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Definition at line 22820 of file RISCVISelLowering.cpp.
References llvm::ISD::ABDS, llvm::ISD::ABDU, DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getVectorElementType(), llvm::SDNode::isUndef(), N, Opc, SDValue(), and Subtarget.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performVWADDSUBW_VLCombine()
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Definition at line 22901 of file RISCVISelLowering.cpp.
References assert(), combineOp_VLToVWOp_VL(), combineVWADDSUBWSelect(), llvm::TargetLowering::DAGCombinerInfo::DAG, N, Opc, Subtarget, and V.
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ performXORCombine()
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Definition at line 20846 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, CC, combineBinOpOfExtractToReduceTree(), combineBinOpToReduce(), combineSelectAndUseCommutative(), combineXorToBitfieldInsert(), DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getOperandCondCode(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), Imm, llvm::isa(), llvm::isAllOnesConstant(), llvm::isOneConstant(), N, llvm::ISD::ROTL, llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SHL, Subtarget, TLI, llvm::ISD::TRUNCATE, V, and llvm::ISD::ZERO_EXTEND.
◆ processVCIXOperands()
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Definition at line 12351 of file RISCVISelLowering.cpp.
References convertToScalableVector(), llvm::SelectionDAG::getBitcast(), getContainerForFixedLengthVector(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getSubtarget(), llvm::MVT::getVectorVT(), Operands, promoteVCIXScalar(), Subtarget, and V.
Referenced by getVCIXISDNodeVOID(), and getVCIXISDNodeWCHAIN().
◆ promoteVCIXScalar()
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Definition at line 12315 of file RISCVISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::MVT::bitsLT(), DL, llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SDValue::getSimpleValueType(), llvm::MachineFunction::getSubtarget(), II, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::isa(), llvm::MVT::isScalarInteger(), Operands, llvm::ISD::SIGN_EXTEND, and Subtarget.
Referenced by processVCIXOperands().
◆ reduceANDOfAtomicLoad()
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Definition at line 20491 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ATOMIC_LOAD, llvm::cast(), llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dyn_cast(), llvm::SelectionDAG::getAtomicLoad(), llvm::AtomicSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::MemSDNode::getSuccessOrdering(), llvm::SDValue::getValue(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::isStrongerThanMonotonic(), llvm::maskTrailingOnes(), N, llvm::TargetLowering::DAGCombinerInfo::recursivelyDeleteUnusedNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), uint64_t, and llvm::ISD::ZEXTLOAD.
Referenced by performANDCombine().
◆ reverseZExtICmpCombine()
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Definition at line 20449 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSetCC(), llvm::EVT::getVectorElementCount(), llvm::EVT::getVectorVT(), llvm::APInt::getZExtValue(), llvm::EVT::isVector(), llvm::PatternMatch::m_And(), llvm::SDPatternMatch::m_ConstInt(), llvm::MIPatternMatch::m_Not(), llvm::PatternMatch::m_One(), llvm::MIPatternMatch::m_OneUse(), llvm::SDPatternMatch::m_Srl(), llvm::PatternMatch::m_Trunc(), llvm::PatternMatch::m_Value(), N, llvm::SDPatternMatch::sd_match(), SDValue(), llvm::ISD::SETEQ, llvm::ISD::SETNE, Subtarget, X, and llvm::ISD::ZERO_EXTEND.
Referenced by performANDCombine().
◆ simplifyOp_VL()
Definition at line 22578 of file RISCVISelLowering.cpp.
References A(), assert(), B(), llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::isConstantSplatVectorAllZeros(), llvm::SDValue::isUndef(), N, and SDValue().
Referenced by llvm::RISCVTargetLowering::PerformDAGCombine().
◆ splatPartsI64WithVL()
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Definition at line 5165 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::cast(), DL, llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorVT(), llvm::Hi, llvm::isa(), llvm::isUInt(), llvm::SDValue::isUndef(), Lo, and llvm::ISD::SRA.
Referenced by splatSplitI64WithVL().
◆ splatSplitI64WithVL()
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Definition at line 5228 of file RISCVISelLowering.cpp.
References assert(), DL, llvm::Hi, Lo, splatPartsI64WithVL(), and llvm::SelectionDAG::SplitScalar().
Referenced by lowerScalarSplat(), and lowerVectorIntrinsicScalars().
◆ SplitStrictFPVectorOp()
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Definition at line 8292 of file RISCVISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::SplitVector(), and V.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ SplitVectorOp()
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Definition at line 8230 of file RISCVISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::GetSplitDestVTs(), and llvm::SelectionDAG::SplitVector().
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ SplitVectorReductionOp()
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Definition at line 8255 of file RISCVISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::ISD::getVecReduceBaseOpcode(), llvm::Hi, Lo, llvm::SelectionDAG::SplitEVL(), llvm::SelectionDAG::SplitVector(), and llvm::ISD::VECREDUCE_SEQ_FADD.
Referenced by llvm::RISCVTargetLowering::LowerOperation().
◆ STATISTIC()
| STATISTIC | ( | NumTailCalls | , |
| "Number of tail calls" | ) |
◆ transformAddImmMulImm()
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Definition at line 19453 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, C0, C1, DL, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getSignedConstant(), llvm::EVT::getSizeInBits(), llvm::SDNode::hasOneUse(), llvm::isInt(), llvm::EVT::isVector(), llvm::ISD::MUL, N, SDValue(), and Subtarget.
Referenced by performADDCombine().
◆ transformAddShlImm()
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Definition at line 19244 of file RISCVISelLowering.cpp.
References C0, C1, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDNode::hasOneUse(), llvm::EVT::isVector(), N, SDValue(), llvm::ISD::SHL, and Subtarget.
Referenced by performADDCombine().
◆ translateSetCCForBranch()
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Definition at line 2973 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, llvm::bit_width(), C(), CC, DL, llvm::dyn_cast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::getSetCCSwappedOperands(), llvm::SelectionDAG::getSignedConstant(), INT64_MAX, llvm::isa(), llvm::isInt(), llvm::isMask_64(), llvm::isNullConstant(), llvm::isPowerOf2_64(), llvm::isUInt(), LHS, llvm::Log2_64(), RHS, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SHL, Subtarget, std::swap(), and uint64_t.
◆ tryDemorganOfBooleanCondition()
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Definition at line 23912 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, Cond, llvm::APInt::getBitsSetFrom(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getOperandCondCode(), llvm::SelectionDAG::getSetCC(), llvm::ISD::getSetCCInverse(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), llvm::isAllOnesConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::EVT::isScalarInteger(), llvm::SelectionDAG::MaskedValueIsZero(), Opc, llvm::ISD::OR, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETLT, std::swap(), llvm::ISD::XOR, and llvm::Xor.
Referenced by combine_CC().
◆ tryFoldSelectIntoOp()
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Definition at line 24107 of file RISCVISelLowering.cpp.
References llvm::ISD::ADD, assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIdentityElement(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSelect(), llvm::SDValue::getValueType(), N, Opc, llvm::ISD::OR, llvm::ISD::ROTL, llvm::ISD::ROTR, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::UMAX, llvm::ISD::UMIN, and llvm::ISD::XOR.
Referenced by performSELECTCombine().
◆ tryMemPairCombine()
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Definition at line 22917 of file RISCVISelLowering.cpp.
References llvm::cast(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::MachineMemOperand::getPointerInfo(), llvm::MachineFunction::getSubtarget(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasPredecessorHelper(), Imm, llvm::ISD::LOAD, llvm::SelectionDAG::ReplaceAllUsesWith(), SDValue(), Subtarget, uint64_t, and llvm::ISD::ZEXTLOAD.
Referenced by performMemPairCombine().
◆ tryWidenMaskForShuffle()
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Try to widen element type to get a new mask value for a better permutation sequence.
This doesn't try to inspect the widened mask for profitability; we speculate the widened form is equal or better. This has the effect of reducing mask constant sizes - allowing cheaper materialization sequences
- and index sequence sizes - reducing register pressure and materialization cost, at the cost of (possibly) an extra VTYPE toggle.
Definition at line 6404 of file RISCVISelLowering.cpp.
References llvm::cast(), DL, llvm::SelectionDAG::getBitcast(), llvm::MVT::getFixedSizeInBits(), llvm::MVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::MVT::getVectorVT(), llvm::MVT::isFloatingPoint(), llvm::TargetLoweringBase::isTypeLegal(), SDValue(), llvm::V1, and llvm::widenShuffleMaskElts().
◆ unpackF64OnRV32DSoftABI()
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Definition at line 28632 of file RISCVISelLowering.cpp.
References assert(), llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getSubtarget(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), Lo, Subtarget, and std::swap().
Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().
◆ unpackFromMemLoc()
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Definition at line 28612 of file RISCVISelLowering.cpp.
References convertLocVTToValVT(), llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getDataLayout(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::DataLayout::getPointerSizeInBits(), llvm::EVT::getStoreSize(), llvm::CCValAssign::Indirect, and TLI.
◆ unpackFromRegLoc()
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Definition at line 28548 of file RISCVISelLowering.cpp.
References llvm::RISCVMachineFunctionInfo::addSExt32Register(), llvm::BitWidth, convertLocVTToValVT(), DL, llvm::Function::getArg(), llvm::SelectionDAG::getCopyFromReg(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::Type::getIntegerBitWidth(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getRegInfo(), llvm::EVT::getSimpleVT(), llvm::Value::getType(), llvm::CCValAssign::Indirect, llvm::Type::isIntegerTy(), and TLI.
◆ unpackGPRVecOnRV32()
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Definition at line 28670 of file RISCVISelLowering.cpp.
References assert(), llvm::MachineFrameInfo::CreateFixedObject(), DL, llvm::SelectionDAG::getCopyFromReg(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::MachineFunction::getRegInfo(), llvm::CCValAssign::getValVT(), llvm::Hi, llvm::CCValAssign::isMemLoc(), llvm::CCValAssign::isRegLoc(), and Lo.
Referenced by llvm::RISCVTargetLowering::LowerFormalArguments().
◆ useInversedSetcc()
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Definition at line 24223 of file RISCVISelLowering.cpp.
References llvm::ISD::AND, CC, Cond, DL, llvm::False, llvm::SelectionDAG::getSelect(), llvm::SelectionDAG::getSetCC(), llvm::isa(), llvm::isNullConstant(), llvm::APInt::isPowerOf2(), llvm::EVT::isScalarInteger(), llvm::APInt::isSignedIntN(), LHS, N, RHS, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, Subtarget, and llvm::True.
Referenced by performSELECTCombine().
◆ useRVVForFixedLengthVectorVT()
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Definition at line 3307 of file RISCVISelLowering.cpp.
References assert(), llvm::divideCeil(), llvm::MVT::getFixedSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::MVT::getVectorNumElements(), llvm::MVT::isFixedLengthVector(), llvm::MVT::isPow2VectorType(), llvm::MVT::SimpleTy, and Subtarget.
Referenced by getContainerForFixedLengthVector().
◆ useTpOffset()
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Definition at line 30867 of file RISCVISelLowering.cpp.
References llvm::IRBuilderBase::CreateCall(), llvm::IRBuilderBase::CreateConstGEP1_32(), llvm::IRBuilderBase::getInt8Ty(), llvm::IRBuilderBase::getModule(), llvm::Intrinsic::getOrInsertDeclaration(), llvm::IRBuilderBase::getPtrTy(), and llvm::Offset.
Referenced by llvm::RISCVTargetLowering::getIRStackGuard().
◆ widenPackedVectorWithZeros()
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Definition at line 17144 of file RISCVISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), V, and Zero.
Referenced by llvm::RISCVTargetLowering::ReplaceNodeResults().
◆ widenVectorOpsToi8()
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Definition at line 15116 of file RISCVISelLowering.cpp.
References assert(), llvm::MVT::changeVectorElementType(), DL, llvm::SmallVectorTemplateCommon< T, typename >::front(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), I, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETNE, llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::ISD::ZERO_EXTEND.
Variable Documentation
◆ m_ReverseEVL
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Matches a reverse shifted right EVL elements, or a vp.reverse.
Definition at line 23247 of file RISCVISelLowering.cpp.
Referenced by performReverseEVLCombine(), and performVP_STORECombine().
◆ ModeMask32
Definition at line 17033 of file RISCVISelLowering.cpp.
◆ ModeMask64
Definition at line 17032 of file RISCVISelLowering.cpp.
◆ ZvfbfaOps
Definition at line 60 of file RISCVISelLowering.cpp.
Referenced by isPromotedOpNeedingSplit(), and llvm::RISCVTargetLowering::RISCVTargetLowering().
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