LLVM 23.0.0git
Enumerations | Functions
llvm::AArch64_AM Namespace Reference

AArch64_AM - AArch64 Addressing Mode Stuff. More...

Enumerations

enum  ShiftExtendType {
  InvalidShiftExtend = -1 , LSL = 0 , LSR , ASR ,
  ROR , MSL , UXTB , UXTH ,
  UXTW , UXTX , SXTB , SXTH ,
  SXTW , SXTX
}

Functions

static bool isSignExtendShiftType (AArch64_AM::ShiftExtendType Type)
 isSignExtendShiftType - Returns true if Type is sign extending.
static const char * getShiftExtendName (AArch64_AM::ShiftExtendType ST)
 getShiftName - Get the string encoding for the shift type.
static AArch64_AM::ShiftExtendType getShiftType (unsigned Imm)
 getShiftType - Extract the shift type.
static unsigned getShiftValue (unsigned Imm)
 getShiftValue - Extract the shift value.
static unsigned getShifterImm (AArch64_AM::ShiftExtendType ST, unsigned Imm)
 getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==> lsr 010 ==> asr 011 ==> ror 100 ==> msl {8-6} = shifter {5-0} = imm
static unsigned getArithShiftValue (unsigned Imm)
 getArithShiftValue - get the arithmetic shift value.
static AArch64_AM::ShiftExtendType getExtendType (unsigned Imm)
 getExtendType - Extract the extend type for operands of arithmetic ops.
static AArch64_AM::ShiftExtendType getArithExtendType (unsigned Imm)
unsigned getExtendEncoding (AArch64_AM::ShiftExtendType ET)
 Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx.
static unsigned getArithExtendImm (AArch64_AM::ShiftExtendType ET, unsigned Imm)
 getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit extend amount {5-3} = shifter {2-0} = imm3
static bool getMemDoShift (unsigned Imm)
 getMemDoShift - Extract the "do shift" flag value for load/store instructions.
static AArch64_AM::ShiftExtendType getMemExtendType (unsigned Imm)
 getExtendType - Extract the extend type for the offset operand of loads/stores.
static unsigned getMemExtendImm (AArch64_AM::ShiftExtendType ET, bool DoShift)
 getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be scaled by the access size shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx {3-1} = shifter {0} = doshift
static uint64_t ror (uint64_t elt, unsigned size)
static bool processLogicalImmediate (uint64_t Imm, unsigned RegSize, uint64_t &Encoding)
 processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size.
static bool isLogicalImmediate (uint64_t imm, unsigned regSize)
 isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the given register size.
static uint64_t encodeLogicalImmediate (uint64_t imm, unsigned regSize)
 encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of the given register size.
static uint64_t decodeLogicalImmediate (uint64_t val, unsigned regSize)
 decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) into the integer value it represents with regSize bits.
static bool isValidDecodeLogicalImmediate (uint64_t val, unsigned regSize)
 isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) is a valid encoding for an integer value with regSize bits.
static float getFPImmFloat (unsigned Imm)
static int getFP16Imm (const APInt &Imm)
 getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value.
static int getFP16Imm (const APFloat &FPImm)
static int getFP32Imm (const APInt &Imm)
 getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
static int getFP32Imm (const APFloat &FPImm)
static int getFP64Imm (const APInt &Imm)
 getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
static int getFP64Imm (const APFloat &FPImm)
static bool isAdvSIMDModImmType1 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType1 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType1 (uint8_t Imm)
static bool isAdvSIMDModImmType2 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType2 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType2 (uint8_t Imm)
static bool isAdvSIMDModImmType3 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType3 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType3 (uint8_t Imm)
static bool isAdvSIMDModImmType4 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType4 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType4 (uint8_t Imm)
static bool isAdvSIMDModImmType5 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType5 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType5 (uint8_t Imm)
static bool isAdvSIMDModImmType6 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType6 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType6 (uint8_t Imm)
static bool isAdvSIMDModImmType7 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType7 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType7 (uint8_t Imm)
static bool isAdvSIMDModImmType8 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType8 (uint8_t Imm)
static uint8_t encodeAdvSIMDModImmType8 (uint64_t Imm)
static bool isAdvSIMDModImmType9 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType9 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType9 (uint8_t Imm)
static bool isAdvSIMDModImmType10 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType10 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType10 (uint8_t Imm)
static bool isAdvSIMDModImmType11 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType11 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType11 (uint8_t Imm)
static bool isAdvSIMDModImmType12 (uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType12 (uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType12 (uint8_t Imm)
template<typename T>
static bool isSVEMaskOfIdenticalElements (int64_t Imm)
 Returns true if Imm is the concatenation of a repeating pattern of type T.
template<typename T>
static bool isSVECpyImm (int64_t Imm)
 Returns true if Imm is valid for CPY/DUP.
template<typename T>
static bool isSVEAddSubImm (int64_t Imm)
 Returns true if Imm is valid for ADD/SUB.
static bool isSVEMoveMaskPreferredLogicalImmediate (int64_t Imm)
 Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.
static bool isAnyMOVZMovAlias (uint64_t Value, int RegWidth)
static bool isMOVZMovAlias (uint64_t Value, int Shift, int RegWidth)
static bool isMOVNMovAlias (uint64_t Value, int Shift, int RegWidth)
static bool isAnyMOVWMovAlias (uint64_t Value, int RegWidth)
static bool isSVECpyDupImm (int SizeInBits, int64_t Val, int32_t &Imm, int32_t &Shift)
static bool isSVELogicalImm (unsigned SizeInBits, uint64_t ImmVal, uint64_t &Encoding)

Detailed Description

AArch64_AM - AArch64 Addressing Mode Stuff.

Enumeration Type Documentation

◆ ShiftExtendType

enum llvm::AArch64_AM::ShiftExtendType
Enumerator
InvalidShiftExtend 
LSL 
LSR 
ASR 
ROR 
MSL 
UXTB 
UXTH 
UXTW 
UXTX 
SXTB 
SXTH 
SXTW 
SXTX 

Definition at line 32 of file AArch64AddressingModes.h.

Function Documentation

◆ decodeAdvSIMDModImmType1()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType1 ( uint8_t Imm)
inlinestatic

Definition at line 473 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType10()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType10 ( uint8_t Imm)
inlinestatic

Definition at line 676 of file AArch64AddressingModes.h.

Referenced by llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), and llvm::AArch64InstPrinter::printSIMDType10Operand().

◆ decodeAdvSIMDModImmType11()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType11 ( uint8_t Imm)
inlinestatic

Definition at line 725 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType12()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType12 ( uint8_t Imm)
inlinestatic

Definition at line 774 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType2()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType2 ( uint8_t Imm)
inlinestatic

Definition at line 488 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType3()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType3 ( uint8_t Imm)
inlinestatic

Definition at line 503 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType4()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType4 ( uint8_t Imm)
inlinestatic

Definition at line 518 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType5()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType5 ( uint8_t Imm)
inlinestatic

Definition at line 534 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType6()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType6 ( uint8_t Imm)
inlinestatic

Definition at line 550 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType7()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType7 ( uint8_t Imm)
inlinestatic

Definition at line 565 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType8()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType8 ( uint8_t Imm)
inlinestatic

Definition at line 576 of file AArch64AddressingModes.h.

◆ decodeAdvSIMDModImmType9()

uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType9 ( uint8_t Imm)
inlinestatic

Definition at line 596 of file AArch64AddressingModes.h.

◆ decodeLogicalImmediate()

uint64_t llvm::AArch64_AM::decodeLogicalImmediate ( uint64_t val,
unsigned regSize )
inlinestatic

decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) into the integer value it represents with regSize bits.

Definition at line 306 of file AArch64AddressingModes.h.

References assert(), llvm::countl_zero(), N, ror(), and llvm::size().

Referenced by llvm::AArch64InstrInfo::analyzeCompare(), getUsefulBitsFromAndWithImmediate(), llvm::AArch64InstrInfo::optimizeCondBranch(), llvm::AArch64InstPrinter::printInst(), llvm::AArch64InstPrinter::printLogicalImm(), and llvm::AArch64InstPrinter::printSVELogicalImm().

◆ encodeAdvSIMDModImmType1()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType1 ( uint64_t Imm)
inlinestatic

Definition at line 469 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm32().

◆ encodeAdvSIMDModImmType10()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType10 ( uint64_t Imm)
inlinestatic

Definition at line 648 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm64().

◆ encodeAdvSIMDModImmType11()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType11 ( uint64_t Imm)
inlinestatic

Definition at line 697 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImmFP().

◆ encodeAdvSIMDModImmType12()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType12 ( uint64_t Imm)
inlinestatic

Definition at line 746 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImmFP().

◆ encodeAdvSIMDModImmType2()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType2 ( uint64_t Imm)
inlinestatic

Definition at line 484 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm32().

◆ encodeAdvSIMDModImmType3()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType3 ( uint64_t Imm)
inlinestatic

Definition at line 499 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm32().

◆ encodeAdvSIMDModImmType4()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType4 ( uint64_t Imm)
inlinestatic

Definition at line 514 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm32().

◆ encodeAdvSIMDModImmType5()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType5 ( uint64_t Imm)
inlinestatic

Definition at line 530 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm16().

◆ encodeAdvSIMDModImmType6()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType6 ( uint64_t Imm)
inlinestatic

Definition at line 546 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm16().

◆ encodeAdvSIMDModImmType7()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType7 ( uint64_t Imm)
inlinestatic

Definition at line 561 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm321s().

◆ encodeAdvSIMDModImmType8()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType8 ( uint64_t Imm)
inlinestatic

Definition at line 581 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm321s().

◆ encodeAdvSIMDModImmType9()

uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType9 ( uint64_t Imm)
inlinestatic

Definition at line 592 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm8().

◆ encodeLogicalImmediate()

uint64_t llvm::AArch64_AM::encodeLogicalImmediate ( uint64_t imm,
unsigned regSize )
inlinestatic

encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of the given register size.

Definition at line 295 of file AArch64AddressingModes.h.

References assert(), and processLogicalImmediate().

Referenced by llvm::AArch64InstrInfo::insertSelect(), optimizeLogicalImm(), and splitDisjointBitmaskImm().

◆ getArithExtendImm()

unsigned llvm::AArch64_AM::getArithExtendImm ( AArch64_AM::ShiftExtendType ET,
unsigned Imm )
inlinestatic

getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit extend amount {5-3} = shifter {2-0} = imm3

Definition at line 183 of file AArch64AddressingModes.h.

References assert(), and getExtendEncoding().

Referenced by llvm::AArch64TargetLowering::EmitAllocateSMESaveBuffer(), llvm::AArch64InstrInfo::insertSelect(), and llvm::AArch64InstrInfo::probedStackAlloc().

◆ getArithExtendType()

AArch64_AM::ShiftExtendType llvm::AArch64_AM::getArithExtendType ( unsigned Imm)
inlinestatic

Definition at line 151 of file AArch64AddressingModes.h.

References getExtendType().

Referenced by llvm::AArch64InstrInfo::canFoldIntoAddrMode(), and llvm::AArch64InstPrinter::printArithExtend().

◆ getArithShiftValue()

unsigned llvm::AArch64_AM::getArithShiftValue ( unsigned Imm)
inlinestatic

getArithShiftValue - get the arithmetic shift value.

Definition at line 131 of file AArch64AddressingModes.h.

Referenced by llvm::AArch64InstrInfo::canFoldIntoAddrMode(), and llvm::AArch64InstPrinter::printArithExtend().

◆ getExtendEncoding()

unsigned llvm::AArch64_AM::getExtendEncoding ( AArch64_AM::ShiftExtendType ET)
inline

Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx.

Definition at line 164 of file AArch64AddressingModes.h.

References llvm_unreachable, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.

Referenced by getArithExtendImm(), and getMemExtendImm().

◆ getExtendType()

AArch64_AM::ShiftExtendType llvm::AArch64_AM::getExtendType ( unsigned Imm)
inlinestatic

getExtendType - Extract the extend type for operands of arithmetic ops.

Definition at line 136 of file AArch64AddressingModes.h.

References assert(), llvm_unreachable, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.

Referenced by getArithExtendType(), getMemExtendType(), and llvm::AArch64InstrInfo::insertSelect().

◆ getFP16Imm() [1/2]

int llvm::AArch64_AM::getFP16Imm ( const APFloat & FPImm)
inlinestatic

Definition at line 399 of file AArch64AddressingModes.h.

References llvm::APFloat::bitcastToAPInt(), and getFP16Imm().

◆ getFP16Imm() [2/2]

int llvm::AArch64_AM::getFP16Imm ( const APInt & Imm)
inlinestatic

getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value.

If the value cannot be represented as an 8-bit floating-point value, then return -1.

Definition at line 380 of file AArch64AddressingModes.h.

Referenced by getFP16Imm(), and llvm::AArch64TargetLowering::isFPImmLegalAsFMov().

◆ getFP32Imm() [1/2]

int llvm::AArch64_AM::getFP32Imm ( const APFloat & FPImm)
inlinestatic

Definition at line 427 of file AArch64AddressingModes.h.

References llvm::APFloat::bitcastToAPInt(), and getFP32Imm().

◆ getFP32Imm() [2/2]

int llvm::AArch64_AM::getFP32Imm ( const APInt & Imm)
inlinestatic

getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.

If the value cannot be represented as an 8-bit floating-point value, then return -1.

Definition at line 406 of file AArch64AddressingModes.h.

Referenced by getFP32Imm(), and llvm::AArch64TargetLowering::isFPImmLegalAsFMov().

◆ getFP64Imm() [1/2]

int llvm::AArch64_AM::getFP64Imm ( const APFloat & FPImm)
inlinestatic

Definition at line 455 of file AArch64AddressingModes.h.

References llvm::APFloat::bitcastToAPInt(), and getFP64Imm().

◆ getFP64Imm() [2/2]

int llvm::AArch64_AM::getFP64Imm ( const APInt & Imm)
inlinestatic

getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.

If the value cannot be represented as an 8-bit floating-point value, then return -1.

Definition at line 434 of file AArch64AddressingModes.h.

Referenced by getFP64Imm(), and llvm::AArch64TargetLowering::isFPImmLegalAsFMov().

◆ getFPImmFloat()

float llvm::AArch64_AM::getFPImmFloat ( unsigned Imm)
inlinestatic

Definition at line 356 of file AArch64AddressingModes.h.

References llvm::bit_cast(), and I.

Referenced by llvm::AArch64InstPrinter::printFPImmOperand().

◆ getMemDoShift()

bool llvm::AArch64_AM::getMemDoShift ( unsigned Imm)
inlinestatic

getMemDoShift - Extract the "do shift" flag value for load/store instructions.

Definition at line 191 of file AArch64AddressingModes.h.

◆ getMemExtendImm()

unsigned llvm::AArch64_AM::getMemExtendImm ( AArch64_AM::ShiftExtendType ET,
bool DoShift )
inlinestatic

getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be scaled by the access size shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx {3-1} = shifter {0} = doshift

Definition at line 213 of file AArch64AddressingModes.h.

References getExtendEncoding().

◆ getMemExtendType()

AArch64_AM::ShiftExtendType llvm::AArch64_AM::getMemExtendType ( unsigned Imm)
inlinestatic

getExtendType - Extract the extend type for the offset operand of loads/stores.

Definition at line 197 of file AArch64AddressingModes.h.

References getExtendType().

◆ getShifterImm()

unsigned llvm::AArch64_AM::getShifterImm ( AArch64_AM::ShiftExtendType ST,
unsigned Imm )
inlinestatic

getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==> lsr 010 ==> asr 011 ==> ror 100 ==> msl {8-6} = shifter {5-0} = imm

Definition at line 111 of file AArch64AddressingModes.h.

References ASR, assert(), llvm_unreachable, LSL, LSR, MSL, and ROR.

Referenced by llvm::AArch64InstrInfo::copyPhysReg(), emitFrameOffsetAdj(), llvm::AArch64_IMM::expandMOVImm(), expandMOVImmSimple(), isWorthFoldingIntoOrrWithShift(), llvm::AArch64RegisterInfo::materializeFrameBaseRegister(), llvm::AArch64InstrInfo::probedStackAlloc(), tryOrrWithShift(), trySequenceOfOnes(), and tryToreplicateChunks().

◆ getShiftExtendName()

const char * llvm::AArch64_AM::getShiftExtendName ( AArch64_AM::ShiftExtendType ST)
inlinestatic

getShiftName - Get the string encoding for the shift type.

Definition at line 65 of file AArch64AddressingModes.h.

References ASR, llvm_unreachable, LSL, LSR, MSL, ROR, SXTB, SXTH, SXTW, SXTX, UXTB, UXTH, UXTW, and UXTX.

Referenced by llvm::AArch64InstPrinter::printArithExtend(), and llvm::AArch64InstPrinter::printShifter().

◆ getShiftType()

AArch64_AM::ShiftExtendType llvm::AArch64_AM::getShiftType ( unsigned Imm)
inlinestatic

getShiftType - Extract the shift type.

Definition at line 86 of file AArch64AddressingModes.h.

References ASR, InvalidShiftExtend, LSL, LSR, MSL, and ROR.

Referenced by llvm::AArch64InstrInfo::canFoldIntoAddrMode(), getUsefulBitsFromOrWithShiftedReg(), llvm::AArch64InstPrinter::printImm8OptLsl(), and llvm::AArch64InstPrinter::printShifter().

◆ getShiftValue()

unsigned llvm::AArch64_AM::getShiftValue ( unsigned Imm)
inlinestatic

getShiftValue - Extract the shift value.

Definition at line 98 of file AArch64AddressingModes.h.

Referenced by llvm::AArch64InstrInfo::canFoldIntoAddrMode(), llvm::AArch64TargetLowering::computeKnownBitsForTargetNode(), getUsefulBitsFromOrWithShiftedReg(), llvm::AArch64InstPrinter::printAddSubImm(), llvm::AArch64InstPrinter::printImm8OptLsl(), and llvm::AArch64InstPrinter::printShifter().

◆ isAdvSIMDModImmType1()

bool llvm::AArch64_AM::isAdvSIMDModImmType1 ( uint64_t Imm)
inlinestatic

Definition at line 464 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm32().

◆ isAdvSIMDModImmType10()

bool llvm::AArch64_AM::isAdvSIMDModImmType10 ( uint64_t Imm)
inlinestatic

Definition at line 606 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm64().

◆ isAdvSIMDModImmType11()

bool llvm::AArch64_AM::isAdvSIMDModImmType11 ( uint64_t Imm)
inlinestatic

Definition at line 690 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImmFP().

◆ isAdvSIMDModImmType12()

bool llvm::AArch64_AM::isAdvSIMDModImmType12 ( uint64_t Imm)
inlinestatic

Definition at line 740 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImmFP().

◆ isAdvSIMDModImmType2()

bool llvm::AArch64_AM::isAdvSIMDModImmType2 ( uint64_t Imm)
inlinestatic

Definition at line 479 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm32().

◆ isAdvSIMDModImmType3()

bool llvm::AArch64_AM::isAdvSIMDModImmType3 ( uint64_t Imm)
inlinestatic

Definition at line 494 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm32().

◆ isAdvSIMDModImmType4()

bool llvm::AArch64_AM::isAdvSIMDModImmType4 ( uint64_t Imm)
inlinestatic

Definition at line 509 of file AArch64AddressingModes.h.

Referenced by preferGPRForFPImm(), and tryAdvSIMDModImm32().

◆ isAdvSIMDModImmType5()

bool llvm::AArch64_AM::isAdvSIMDModImmType5 ( uint64_t Imm)
inlinestatic

Definition at line 524 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm16().

◆ isAdvSIMDModImmType6()

bool llvm::AArch64_AM::isAdvSIMDModImmType6 ( uint64_t Imm)
inlinestatic

Definition at line 540 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm16().

◆ isAdvSIMDModImmType7()

bool llvm::AArch64_AM::isAdvSIMDModImmType7 ( uint64_t Imm)
inlinestatic

Definition at line 556 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm321s().

◆ isAdvSIMDModImmType8()

bool llvm::AArch64_AM::isAdvSIMDModImmType8 ( uint64_t Imm)
inlinestatic

Definition at line 571 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm321s().

◆ isAdvSIMDModImmType9()

bool llvm::AArch64_AM::isAdvSIMDModImmType9 ( uint64_t Imm)
inlinestatic

Definition at line 586 of file AArch64AddressingModes.h.

Referenced by tryAdvSIMDModImm8().

◆ isAnyMOVWMovAlias()

bool llvm::AArch64_AM::isAnyMOVWMovAlias ( uint64_t Value,
int RegWidth )
inlinestatic

Definition at line 875 of file AArch64AddressingModes.h.

References isAnyMOVZMovAlias().

Referenced by llvm::AArch64InstPrinter::printInst().

◆ isAnyMOVZMovAlias()

bool llvm::AArch64_AM::isAnyMOVZMovAlias ( uint64_t Value,
int RegWidth )
inlinestatic

Definition at line 844 of file AArch64AddressingModes.h.

Referenced by isAnyMOVWMovAlias(), and isMOVNMovAlias().

◆ isLogicalImmediate()

bool llvm::AArch64_AM::isLogicalImmediate ( uint64_t imm,
unsigned regSize )
inlinestatic

isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the given register size.

Return false otherwise.

Definition at line 288 of file AArch64AddressingModes.h.

References processLogicalImmediate().

Referenced by llvm::AArch64TTIImpl::getIntImmCost(), if(), isSVEMoveMaskPreferredLogicalImmediate(), optimizeLogicalImm(), llvm::AArch64TargetLowering::shouldConvertConstantLoadToIntImm(), splitDisjointBitmaskImm(), and tryBitfieldInsertOpFromOrAndImm().

◆ isMOVNMovAlias()

bool llvm::AArch64_AM::isMOVNMovAlias ( uint64_t Value,
int Shift,
int RegWidth )
inlinestatic

Definition at line 863 of file AArch64AddressingModes.h.

References isAnyMOVZMovAlias(), and isMOVZMovAlias().

Referenced by llvm::AArch64InstPrinter::printInst().

◆ isMOVZMovAlias()

bool llvm::AArch64_AM::isMOVZMovAlias ( uint64_t Value,
int Shift,
int RegWidth )
inlinestatic

Definition at line 852 of file AArch64AddressingModes.h.

Referenced by isMOVNMovAlias(), and llvm::AArch64InstPrinter::printInst().

◆ isSignExtendShiftType()

bool llvm::AArch64_AM::isSignExtendShiftType ( AArch64_AM::ShiftExtendType Type)
inlinestatic

isSignExtendShiftType - Returns true if Type is sign extending.

Definition at line 52 of file AArch64AddressingModes.h.

References SXTB, SXTH, SXTW, and SXTX.

◆ isSVEAddSubImm()

template<typename T>
bool llvm::AArch64_AM::isSVEAddSubImm ( int64_t Imm)
inlinestatic

Returns true if Imm is valid for ADD/SUB.

Definition at line 820 of file AArch64AddressingModes.h.

◆ isSVECpyDupImm()

bool llvm::AArch64_AM::isSVECpyDupImm ( int SizeInBits,
int64_t Val,
int32_t & Imm,
int32_t & Shift )
inlinestatic

Definition at line 887 of file AArch64AddressingModes.h.

Referenced by trySVESplat64().

◆ isSVECpyImm()

template<typename T>
bool llvm::AArch64_AM::isSVECpyImm ( int64_t Imm)
inlinestatic

Returns true if Imm is valid for CPY/DUP.

Definition at line 797 of file AArch64AddressingModes.h.

References llvm::max(), and T.

Referenced by isSVEMoveMaskPreferredLogicalImmediate().

◆ isSVELogicalImm()

bool llvm::AArch64_AM::isSVELogicalImm ( unsigned SizeInBits,
uint64_t ImmVal,
uint64_t & Encoding )
inlinestatic

Definition at line 917 of file AArch64AddressingModes.h.

References llvm_unreachable, and processLogicalImmediate().

Referenced by trySVESplat64().

◆ isSVEMaskOfIdenticalElements()

template<typename T>
bool llvm::AArch64_AM::isSVEMaskOfIdenticalElements ( int64_t Imm)
inlinestatic

Returns true if Imm is the concatenation of a repeating pattern of type T.

Definition at line 790 of file AArch64AddressingModes.h.

References llvm::all_equal(), llvm::bit_cast(), and T.

Referenced by isSVEMoveMaskPreferredLogicalImmediate().

◆ isSVEMoveMaskPreferredLogicalImmediate()

bool llvm::AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate ( int64_t Imm)
inlinestatic

Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent.

Definition at line 827 of file AArch64AddressingModes.h.

References B(), llvm::bit_cast(), H, isLogicalImmediate(), isSVECpyImm(), and isSVEMaskOfIdenticalElements().

◆ isValidDecodeLogicalImmediate()

bool llvm::AArch64_AM::isValidDecodeLogicalImmediate ( uint64_t val,
unsigned regSize )
inlinestatic

isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) is a valid encoding for an integer value with regSize bits.

Definition at line 334 of file AArch64AddressingModes.h.

References llvm::countl_zero(), N, and llvm::size().

Referenced by DecodeLogicalImmInstruction(), and DecodeSVELogicalImmInstruction().

◆ processLogicalImmediate()

bool llvm::AArch64_AM::processLogicalImmediate ( uint64_t Imm,
unsigned RegSize,
uint64_t & Encoding )
inlinestatic

processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size.

If so, return true with "encoding" set to the encoded value in the form N:immr:imms.

Definition at line 226 of file AArch64AddressingModes.h.

References assert(), llvm::countl_one(), llvm::countr_one(), llvm::countr_zero(), I, llvm::isShiftedMask_64(), N, RegSize, and Size.

Referenced by canUseOrr(), encodeLogicalImmediate(), llvm::AArch64_IMM::expandMOVImm(), isLogicalImmediate(), isSVELogicalImm(), tryAndOfLogicalImmediates(), tryEorOfLogicalImmediates(), tryOrrOfLogicalImmediates(), and trySequenceOfOnes().

◆ ror()

uint64_t llvm::AArch64_AM::ror ( uint64_t elt,
unsigned size )
inlinestatic

Definition at line 218 of file AArch64AddressingModes.h.

References llvm::size().

Referenced by decodeLogicalImmediate().

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