#include "PPCISelLowering.h"
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "MCTargetDesc/PPCPredicates.h"
#include "PPC.h"
#include "PPCCallingConv.h"
#include "PPCFrameLowering.h"
#include "PPCInstrInfo.h"
#include "PPCMachineFunctionInfo.h"
#include "PPCPerfectShuffle.h"
#include "PPCRegisterInfo.h"
#include "PPCSelectionDAGInfo.h"
#include "PPCSubtarget.h"
#include "PPCTargetMachine.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/APSInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsPowerPC.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Use.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCSectionXCOFF.h"
#include "llvm/MC/MCSymbolXCOFF.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <list>
#include <optional>
#include <utility>
#include <vector>
#include "PPCGenAsmMatcher.inc"

Macros
#define	DEBUG_TYPE "ppc-lowering"
#define	GET_REGISTER_MATCHER

Typedefs
using	LXVKQPattern = std::tuple<uint32_t, uint8_t>

Functions
	STATISTIC (NumTailCalls, "Number of tail calls")
	STATISTIC (NumSiblingCalls, "Number of sibling calls")
	STATISTIC (ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM or XXPERM")
	STATISTIC (NumDynamicAllocaProbed, "Number of dynamic stack allocation probed")
static bool	isNByteElemShuffleMask (ShuffleVectorSDNode *N, unsigned Width, int StepLen)
	Check that the mask is shuffling N byte elements.
static SDValue	widenVec (SelectionDAG &DAG, SDValue Vec, const SDLoc &dl)
static void	signExtendOperandIfUnknown (MachineInstr &MI, MachineBasicBlock BB, unsigned OpIdx, bool IsByte, const PPCInstrInfo TII)
static void	getMaxByValAlign (Type *Ty, Align &MaxAlign, Align MaxMaxAlign)
	getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.
static bool	isFloatingPointZero (SDValue Op)
	isFloatingPointZero - Return true if this is 0.0 or -0.0.
static bool	isConstantOrUndef (int Op, int Val)
	isConstantOrUndef - Op is either an undef node or a ConstantSDNode.
static bool	isVMerge (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned LHSStart, unsigned RHSStart)
	isVMerge - Common function, used to match vmrg* shuffles.
static bool	isVMerge (ShuffleVectorSDNode *N, unsigned IndexOffset, unsigned RHSStartValue)
	Common function used to match vmrgew and vmrgow shuffles.
static bool	isXXBRShuffleMaskHelper (ShuffleVectorSDNode *N, int Width)
static bool	provablyDisjointOr (SelectionDAG &DAG, const SDValue &N)
	Used when computing address flags for selecting loads and stores.
static void	fixupFuncForFI (SelectionDAG &DAG, int FrameIdx, EVT VT)
template<typename Ty>
static bool	isValidPCRelNode (SDValue N)
static bool	usePartialVectorLoads (SDNode *N, const PPCSubtarget &ST)
	Returns true if we should use a direct load into vector instruction (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
static void	getLabelAccessInfo (bool IsPIC, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
	Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
static SDValue	LowerLabelRef (SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)
static void	setUsesTOCBasePtr (MachineFunction &MF)
static void	setUsesTOCBasePtr (SelectionDAG &DAG)
static void	updateForAIXShLibTLSModelOpt (TLSModel::Model &Model, SelectionDAG &DAG, const TargetMachine &TM)
	updateForAIXShLibTLSModelOpt - Helper to initialize TLS model opt settings, and then apply the update.
static unsigned	CalculateStackSlotSize (EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
	CalculateStackSlotSize - Calculates the size reserved for this argument on the stack.
static Align	CalculateStackSlotAlignment (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
	CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack.
static bool	CalculateStackSlotUsed (EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize, unsigned LinkageSize, unsigned ParamAreaSize, unsigned &ArgOffset, unsigned &AvailableFPRs, unsigned &AvailableVRs)
	CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers).
static unsigned	EnsureStackAlignment (const PPCFrameLowering *Lowering, unsigned NumBytes)
	EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target.
static int	CalculateTailCallSPDiff (SelectionDAG &DAG, bool isTailCall, unsigned ParamSize)
	CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall.
static bool	isFunctionGlobalAddress (const GlobalValue *CalleeGV)
static bool	callsShareTOCBase (const Function Caller, const GlobalValue CalleeGV, const TargetMachine &TM)
static bool	needStackSlotPassParameters (const PPCSubtarget &Subtarget, const SmallVectorImpl< ISD::OutputArg > &Outs)
static bool	hasSameArgumentList (const Function *CallerFn, const CallBase &CB)
static bool	areCallingConvEligibleForTCO_64SVR4 (CallingConv::ID CallerCC, CallingConv::ID CalleeCC)
static SDNode *	isBLACompatibleAddress (SDValue Op, SelectionDAG &DAG)
	isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction.
static void	StoreTailCallArgumentsToStackSlot (SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl< TailCallArgumentInfo > &TailCallArgs, SmallVectorImpl< SDValue > &MemOpChains, const SDLoc &dl)
	StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
static SDValue	EmitTailCallStoreFPAndRetAddr (SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl)
	EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call.
static void	CalculateTailCallArgDest (SelectionDAG &DAG, MachineFunction &MF, bool IsPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
	CalculateTailCallArgDest - Remember Argument for later processing.
static SDValue	CreateCopyOfByValArgument (SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
	CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size".
static void	LowerMemOpCallTo (SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
	LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls.
static void	PrepareTailCall (SelectionDAG &DAG, SDValue &InGlue, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
static bool	isIndirectCall (const SDValue &Callee, SelectionDAG &DAG, const PPCSubtarget &Subtarget, bool isPatchPoint)
static bool	isTOCSaveRestoreRequired (const PPCSubtarget &Subtarget)
static unsigned	getCallOpcode (PPCTargetLowering::CallFlags CFlags, const Function &Caller, const SDValue &Callee, const PPCSubtarget &Subtarget, const TargetMachine &TM, bool IsStrictFPCall=false)
static SDValue	transformCallee (const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget)
static SDValue	getOutputChainFromCallSeq (SDValue CallSeqStart)
static void	prepareIndirectCall (SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, const SDLoc &dl)
static void	prepareDescriptorIndirectCall (SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, const CallBase *CB, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget)
static void	prepareOutOfLineGlueCall (SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, const CallBase *CB, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget)
static void	buildCallOperands (SmallVectorImpl< SDValue > &Ops, PPCTargetLowering::CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, SmallVector< std::pair< unsigned, SDValue >, 8 > &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget)
static bool	isGPRShadowAligned (MCPhysReg Reg, Align RequiredAlign)
static bool	CC_AIX (unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)
static const TargetRegisterClass *	getRegClassForSVT (MVT::SimpleValueType SVT, bool IsPPC64, bool HasP8Vector, bool HasVSX)
static SDValue	truncateScalarIntegerArg (ISD::ArgFlagsTy Flags, EVT ValVT, SelectionDAG &DAG, SDValue ArgValue, MVT LocVT, const SDLoc &dl)
static unsigned	mapArgRegToOffsetAIX (unsigned Reg, const PPCFrameLowering *FL)
static unsigned	getPPCStrictOpcode (unsigned Opc)
static SDValue	convertFPToInt (SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static SDValue	convertIntToFP (SDValue Op, SDValue Src, SelectionDAG &DAG, const PPCSubtarget &Subtarget, SDValue Chain=SDValue())
static SDValue	getCanonicalConstSplat (uint64_t Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
	getCanonicalConstSplat - Build a canonical splat immediate of Val with an element size of SplatSize.
static SDValue	BuildIntrinsicOp (unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
	BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID.
static SDValue	BuildIntrinsicOp (unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
	BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID.
static SDValue	BuildIntrinsicOp (unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
	BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID.
static SDValue	BuildVSLDOI (SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
	BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount.
static bool	haveEfficientBuildVectorPattern (BuildVectorSDNode *V, bool HasDirectMove, bool HasP8Vector)
	Do we have an efficient pattern in a .td file for this node?
static const SDValue *	getNormalLoadInput (const SDValue &Op, bool &IsPermuted)
static bool	isValidSplatLoad (const PPCSubtarget &Subtarget, const SDValue &Op, unsigned &Opcode)
bool	isValidMtVsrBmi (APInt &BitMask, BuildVectorSDNode &BVN, bool IsLittleEndian)
static SDValue	GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
	GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
static bool	getVectorCompareInfo (SDValue Intrin, int &CompareOpc, bool &isDot, const PPCSubtarget &Subtarget)
	getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison.
static SDValue	getDataClassTest (SDValue Op, FPClassTest Mask, const SDLoc &Dl, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static SDValue	AdjustLength (SDValue Val, unsigned Bits, bool Left, SelectionDAG &DAG)
static SDValue	ConvertCarryValueToCarryFlag (EVT SumType, SDValue Value, SelectionDAG &DAG, const PPCSubtarget &STI)
static SDValue	ConvertCarryFlagToCarryValue (EVT SumType, SDValue Flag, EVT CarryType, SelectionDAG &DAG, const PPCSubtarget &STI)
static Instruction *	callIntrinsic (IRBuilderBase &Builder, Intrinsic::ID Id)
static bool	isSignExtended (MachineInstr &MI, const PPCInstrInfo *TII)
static bool	IsSelect (unsigned Opcode, bool CheckOnlyCC=false)
	Check if the opcode is a SELECT or SELECT_CC variant.
static bool	IsSelectCC (unsigned Opcode)
static MachineBasicBlock *	emitSelect (MachineInstr &MI, MachineBasicBlock BB, const TargetInstrInfo TII, const PPCSubtarget &Subtarget)
	Emit SELECT instruction, using ISEL if available, otherwise use branch-based control flow.
static void	createAtomicLoopBlocks (MachineFunction F, MachineBasicBlock BB, MachineBasicBlock &loop1MBB, MachineBasicBlock &loop2MBB, MachineBasicBlock *&exitMBB, MachineInstr &MI, MachineFunction::iterator It)
	Helper function to create basic blocks for atomic compare-and-swap.
static MachineBasicBlock *	emitAtomicCmpSwapHardware (MachineInstr &MI, MachineBasicBlock BB, const TargetInstrInfo TII, const PPCSubtarget &Subtarget)
	Emit hardware-supported atomic compare-and-swap for I32/I64 and I8/I16 with partword atomic support.
static MachineBasicBlock *	emitAtomicCmpSwapSoftware (MachineInstr &MI, MachineBasicBlock BB, const TargetInstrInfo TII, const PPCSubtarget &Subtarget)
	Emit software-emulated atomic compare-and-swap for I8/I16 without hardware partword atomic support.
static int	getEstimateRefinementSteps (EVT VT, const PPCSubtarget &Subtarget)
static void	getBaseWithConstantOffset (SDValue Loc, SDValue &Base, int64_t &Offset, SelectionDAG &DAG)
static bool	isConsecutiveLSLoc (SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
static bool	isConsecutiveLS (SDNode N, LSBaseSDNode Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
static bool	findConsecutiveLoad (LoadSDNode *LD, SelectionDAG &DAG)
static SDValue	generateEquivalentSub (SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG)
	This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR.
static bool	canConvertToVcmpequb (SDValue &LHS, SDValue &RHS, bool IsPPC64)
SDValue	convertTwoLoadsAndCmpToVCMPEQUB (SelectionDAG &DAG, SDNode *N, const SDLoc &DL)
static bool	canConvertSETCCToXori (SDNode *N)
static SDValue	ConvertSETCCToXori (SDNode *N, SelectionDAG &DAG)
static bool	isFPExtLoad (SDValue Op)
static std::optional< LXVKQPattern >	getPatternInfo (const APInt &FullVal)
static SDValue	combineBVOfConsecutiveLoads (SDNode *N, SelectionDAG &DAG)
	Reduce the number of loads when building a vector.
static SDValue	addShuffleForVecExtend (SDNode *N, SelectionDAG &DAG, SDValue Input, uint64_t Elems, uint64_t CorrectElems)
static SDValue	combineBVOfVecSExt (SDNode *N, SelectionDAG &DAG)
static SDValue	combineBVZEXTLOAD (SDNode *N, SelectionDAG &DAG)
static bool	isAlternatingShuffMask (const ArrayRef< int > &Mask, int NumElts)
static bool	isSplatBV (SDValue Op)
static SDValue	isScalarToVec (SDValue Op)
static void	fixupShuffleMaskForPermutedSToV (SmallVectorImpl< int > &ShuffV, int LHSFirstElt, int LHSLastElt, int RHSFirstElt, int RHSLastElt, int HalfVec, unsigned LHSNumValidElts, unsigned RHSNumValidElts, const PPCSubtarget &Subtarget)
static SDValue	getSToVPermuted (SDValue OrigSToV, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static bool	isShuffleMaskInRange (const SmallVectorImpl< int > &ShuffV, int HalfVec, int LHSLastElementDefined, int RHSLastElementDefined)
static SDValue	generateSToVPermutedForVecShuffle (int ScalarSize, uint64_t ShuffleEltWidth, unsigned &NumValidElts, int FirstElt, int &LastElt, SDValue VecShuffOperand, SDValue SToVNode, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static bool	isStoreConditional (SDValue Intrin, unsigned &StoreWidth)
static SDValue	DAGCombineAddc (SDNode *N, llvm::PPCTargetLowering::DAGCombinerInfo &DCI)
static SDValue	combineSELECT_CCBitFloor (SDNode *N, SelectionDAG &DAG)
	Optimize the bitfloor(X) pattern for PowerPC.
static SDValue	combineZextSetccWithZero (SDNode *N, SelectionDAG &DAG)
static SDValue	combineXorSelectCC (SDNode *N, SelectionDAG &DAG)
static unsigned	invertFMAOpcode (unsigned Opc)
static SDValue	stripModuloOnShift (const TargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
static SDValue	combineADDToADDZE (SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static SDValue	combineADDToMAT_PCREL_ADDR (SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static SDValue	combineADDToSUB (SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static void	setAlignFlagsForFI (SDValue N, unsigned &FlagSet, SelectionDAG &DAG)
	Set alignment flags based on whether or not the Frame Index is aligned.
static void	computeFlagsForAddressComputation (SDValue N, unsigned &FlagSet, SelectionDAG &DAG)
	Given a node, compute flags that are used for address computation when selecting load and store instructions.
static bool	isPCRelNode (SDValue N)
static void	setXFormForUnalignedFI (SDValue N, unsigned Flags, PPC::AddrMode &Mode)
static Intrinsic::ID	getIntrinsicForAtomicRMWBinOp128 (AtomicRMWInst::BinOp BinOp)

Variables
static cl::opt< bool >	DisableP10StoreForward ("disable-p10-store-forward", cl::desc("disable P10 store forward-friendly conversion"), cl::Hidden, cl::init(false))
static cl::opt< bool >	DisablePPCPreinc ("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)
static cl::opt< bool >	DisableILPPref ("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)
static cl::opt< bool >	DisablePPCUnaligned ("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)
static cl::opt< bool >	DisableSCO ("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden)
static cl::opt< bool >	DisableInnermostLoopAlign32 ("disable-ppc-innermost-loop-align32", cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden)
static cl::opt< bool >	UseAbsoluteJumpTables ("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden)
static cl::opt< bool >	DisablePerfectShuffle ("ppc-disable-perfect-shuffle", cl::desc("disable vector permute decomposition"), cl::init(true), cl::Hidden)
cl::opt< bool >	DisableAutoPairedVecSt ("disable-auto-paired-vec-st", cl::desc("disable automatically generated 32byte paired vector stores"), cl::init(true), cl::Hidden)
static cl::opt< unsigned >	PPCMinimumJumpTableEntries ("ppc-min-jump-table-entries", cl::init(64), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on PPC"))
static cl::opt< unsigned >	PPCMinimumBitTestCmps ("ppc-min-bit-test-cmps", cl::init(3), cl::Hidden, cl::desc("Set minimum of largest number of comparisons to use bit test for " "switch on PPC."))
static cl::opt< unsigned >	PPCGatherAllAliasesMaxDepth ("ppc-gather-alias-max-depth", cl::init(18), cl::Hidden, cl::desc("max depth when checking alias info in GatherAllAliases()"))
static cl::opt< unsigned >	PPCAIXTLSModelOptUseIEForLDLimit ("ppc-aix-shared-lib-tls-model-opt-limit", cl::init(1), cl::Hidden, cl::desc("Set inclusive limit count of TLS local-dynamic access(es) in a " "function to use initial-exec"))
constexpr uint64_t	AIXSmallTlsPolicySizeLimit = 32751
cl::opt< bool >	ANDIGlueBug
static const MCPhysReg	FPR []
	FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "ppc-lowering"

Definition at line 103 of file PPCISelLowering.cpp.

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 19096 of file PPCISelLowering.cpp.

Typedef Documentation

◆ LXVKQPattern

using LXVKQPattern = std::tuple<uint32_t, uint8_t>

Definition at line 16256 of file PPCISelLowering.cpp.

Function Documentation

◆ addShuffleForVecExtend()

SDValue addShuffleForVecExtend	(	SDNode *	N,
		SelectionDAG &	DAG,
		SDValue	Input,
		uint64_t	Elems,
		uint64_t	CorrectElems )

static

Definition at line 16489 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), llvm::DataLayout::isLittleEndian(), N, and llvm::ISD::SIGN_EXTEND_INREG.

Referenced by combineBVOfVecSExt().

◆ AdjustLength()

SDValue AdjustLength	(	SDValue	Val,
		unsigned	Bits,
		bool	Left,
		SelectionDAG &	DAG )

static

Definition at line 11943 of file PPCISelLowering.cpp.

References llvm::countr_zero(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::Left, and llvm::ISD::SHL.

◆ areCallingConvEligibleForTCO_64SVR4()

bool areCallingConvEligibleForTCO_64SVR4	(	CallingConv::ID	CallerCC,
		CallingConv::ID	CalleeCC )

static

Definition at line 4958 of file PPCISelLowering.cpp.

References llvm::CallingConv::C, and llvm::CallingConv::Fast.

◆ buildCallOperands()

void buildCallOperands	(	SmallVectorImpl< SDValue > &	Ops,
		PPCTargetLowering::CallFlags	CFlags,
		const SDLoc &	dl,
		SelectionDAG &	DAG,
		SmallVector< std::pair< unsigned, SDValue >, 8 > &	RegsToPass,
		SDValue	Glue,
		SDValue	Chain,
		SDValue &	Callee,
		int	SPDiff,
		const PPCSubtarget &	Subtarget )

static

Definition at line 5648 of file PPCISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, assert(), llvm::PPCTargetLowering::CallFlags::CallConv, llvm::SelectionDAG::getConstant(), llvm::PPCSubtarget::getEnvironmentPointerRegister(), llvm::PPCSubtarget::getFrameLowering(), llvm::PPCSubtarget::getGlueCodeDescriptorRegister(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::PPCSubtarget::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::PPCSubtarget::getScalarIntVT(), llvm::PPCSubtarget::getStackPointerRegister(), llvm::PPCSubtarget::getTOCPointerRegister(), llvm::PPCFrameLowering::getTOCSaveOffset(), llvm::PPCTargetLowering::CallFlags::HasNest, llvm::PPCSubtarget::is32BitELFABI(), llvm::PPCSubtarget::is64BitELFABI(), llvm::PPCSubtarget::isAIXABI(), llvm::PPCTargetLowering::CallFlags::IsIndirect, llvm::PPCTargetLowering::CallFlags::IsPatchPoint, llvm::PPCTargetLowering::CallFlags::IsTailCall, isTOCSaveRestoreRequired(), llvm::PPCSubtarget::isUsingPCRelativeCalls(), llvm::PPCTargetLowering::CallFlags::IsVarArg, N, Reg, TRI, and llvm::PPCSubtarget::usesFunctionDescriptors().

◆ BuildIntrinsicOp() [1/3]

SDValue BuildIntrinsicOp	(	unsigned	IID,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const SDLoc &	dl,
		EVT	DestVT = MVT::Other )

static

BuildIntrinsicOp - Return a binary operator intrinsic node with the specified intrinsic ID.

Definition at line 9369 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, and RHS.

◆ BuildIntrinsicOp() [2/3]

SDValue BuildIntrinsicOp	(	unsigned	IID,
		SDValue	Op,
		SelectionDAG &	DAG,
		const SDLoc &	dl,
		EVT	DestVT = MVT::Other )

static

BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID.

Definition at line 9360 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::ISD::INTRINSIC_WO_CHAIN.

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ BuildIntrinsicOp() [3/3]

SDValue BuildIntrinsicOp	(	unsigned	IID,
		SDValue	Op0,
		SDValue	Op1,
		SDValue	Op2,
		SelectionDAG &	DAG,
		const SDLoc &	dl,
		EVT	DestVT = MVT::Other )

static

BuildIntrinsicOp - Return a ternary operator intrinsic node with the specified intrinsic ID.

Definition at line 9379 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), and llvm::ISD::INTRINSIC_WO_CHAIN.

◆ BuildVSLDOI()

SDValue BuildVSLDOI	(	SDValue	LHS,
		SDValue	RHS,
		unsigned	Amt,
		EVT	VT,
		SelectionDAG &	DAG,
		const SDLoc &	dl )

static

BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount.

The result has the specified value type.

Definition at line 9389 of file PPCISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), LHS, RHS, and T.

Referenced by GeneratePerfectShuffle().

◆ CalculateStackSlotAlignment()

Align CalculateStackSlotAlignment	(	EVT	ArgVT,
		EVT	OrigVT,
		ISD::ArgFlagsTy	Flags,
		unsigned	PtrByteSize )

static

CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack.

Definition at line 4047 of file PPCISelLowering.cpp.

References llvm::EVT::getStoreSize(), and llvm_unreachable.

Referenced by CalculateStackSlotUsed().

◆ CalculateStackSlotSize()

unsigned CalculateStackSlotSize	(	EVT	ArgVT,
		ISD::ArgFlagsTy	Flags,
		unsigned	PtrByteSize )

static

CalculateStackSlotSize - Calculates the size reserved for this argument on the stack.

Definition at line 4031 of file PPCISelLowering.cpp.

References llvm::EVT::getStoreSize().

Referenced by CalculateStackSlotUsed().

◆ CalculateStackSlotUsed()

bool CalculateStackSlotUsed	(	EVT	ArgVT,
		EVT	OrigVT,
		ISD::ArgFlagsTy	Flags,
		unsigned	PtrByteSize,
		unsigned	LinkageSize,
		unsigned	ParamAreaSize,
		unsigned &	ArgOffset,
		unsigned &	AvailableFPRs,
		unsigned &	AvailableVRs )

static

CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passed in registers).

ArgOffset, AvailableFPRs, and AvailableVRs must hold the current argument position, and will be updated to account for this argument.

Definition at line 4089 of file PPCISelLowering.cpp.

References llvm::alignTo(), CalculateStackSlotAlignment(), and CalculateStackSlotSize().

Referenced by needStackSlotPassParameters().

◆ CalculateTailCallArgDest()

void CalculateTailCallArgDest	(	SelectionDAG &	DAG,
		MachineFunction &	MF,
		bool	IsPPC64,
		SDValue	Arg,
		int	SPDiff,
		unsigned	ArgOffset,
		SmallVectorImpl< TailCallArgumentInfo > &	TailCallArguments )

static

CalculateTailCallArgDest - Remember Argument for later processing.

Calculate the position of the argument.

Definition at line 5161 of file PPCISelLowering.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::SDValue::getValueSizeInBits(), llvm::Offset, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by LowerMemOpCallTo().

◆ CalculateTailCallSPDiff()

int CalculateTailCallSPDiff	(	SelectionDAG &	DAG,
		bool	isTailCall,
		unsigned	ParamSize )

static

CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the arguments for the tailcall.

Definition at line 4796 of file PPCISelLowering.cpp.

References llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::PPCFunctionInfo::getMinReservedArea(), and llvm::PPCFunctionInfo::setTailCallSPDelta().

◆ callIntrinsic()

Instruction * callIntrinsic	(	IRBuilderBase &	Builder,
		Intrinsic::ID	Id )

static

Definition at line 13021 of file PPCISelLowering.cpp.

Referenced by llvm::PPCTargetLowering::emitLeadingFence(), and llvm::PPCTargetLowering::emitTrailingFence().

◆ callsShareTOCBase()

bool callsShareTOCBase	(	const Function *	Caller,
		const GlobalValue *	CalleeGV,
		const TargetMachine &	TM )

static

Definition at line 4813 of file PPCISelLowering.cpp.

References assert(), llvm::dyn_cast(), F, llvm::GlobalAlias::getAliaseeObject(), llvm::TargetMachine::getCodeModel(), llvm::TargetMachine::getFunctionSections(), llvm::GlobalValue::getSection(), llvm::TargetMachine::getSubtarget(), llvm::GlobalValue::hasComdat(), llvm::GlobalValue::isStrongDefinitionForLinker(), llvm::PPCSubtarget::isUsingPCRelativeCalls(), llvm::CodeModel::Large, llvm::CodeModel::Medium, and llvm::TargetMachine::shouldAssumeDSOLocal().

Referenced by getCallOpcode().

◆ canConvertSETCCToXori()

bool canConvertSETCCToXori ( SDNode * N )

static

Definition at line 15973 of file PPCISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::CallingConv::C, llvm::cast(), llvm::dyn_cast(), LHS, N, RHS, llvm::ISD::SETCC, and llvm::ISD::SETEQ.

◆ canConvertToVcmpequb()

bool canConvertToVcmpequb	(	SDValue &	LHS,
		SDValue &	RHS,
		bool	IsPPC64 )

static

Definition at line 15833 of file PPCISelLowering.cpp.

References llvm::CallingConv::C, llvm::cast(), llvm::ISD::Constant, llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), LHS, llvm::ISD::NON_EXTLOAD, RHS, llvm::APInt::ult(), and llvm::ISD::UNINDEXED.

◆ CC_AIX()

bool CC_AIX	(	unsigned	ValNo,
		MVT	ValVT,
		MVT	LocVT,
		CCValAssign::LocInfo	LocInfo,
		ISD::ArgFlagsTy	ArgFlags,
		Type *	OrigTy,
		CCState &	State )

static

◆ combineADDToADDZE()

SDValue combineADDToADDZE	(	SDNode *	N,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget )

static

◆ combineADDToMAT_PCREL_ADDR()

SDValue combineADDToMAT_PCREL_ADDR	(	SDNode *	N,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget )

static

Definition at line 19974 of file PPCISelLowering.cpp.

References DL, llvm::dyn_cast(), llvm::GlobalAddressSDNode::getGlobal(), llvm::SelectionDAG::getNode(), llvm::GlobalAddressSDNode::getOffset(), llvm::ConstantSDNode::getSExtValue(), llvm::GlobalAddressSDNode::getTargetFlags(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDNode::getValueType(), llvm::isInt(), llvm::PPCSubtarget::isUsingPCRelativeCalls(), LHS, N, RHS, SDValue(), and std::swap().

◆ combineADDToSUB()

SDValue combineADDToSUB	(	SDNode *	N,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget )

static

Definition at line 20020 of file PPCISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, DL, llvm::dyn_cast(), llvm::APInt::getAllOnes(), llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), LHS, N, RHS, SDValue(), and llvm::ISD::SUB.

◆ combineBVOfConsecutiveLoads()

SDValue combineBVOfConsecutiveLoads	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Reduce the number of loads when building a vector.

Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. If the loads are consecutive but in descending order, a shuffle is added at the end to reorder the vector.

Definition at line 16391 of file PPCISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::SelectionDAG::areNonVolatileConsecutiveLoads(), assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::ISD::BUILD_VECTOR, llvm::cast(), llvm::ISD::EXTLOAD, llvm::ISD::FP_ROUND, llvm::MemSDNode::getAlign(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getVectorShuffle(), llvm::ISD::LOAD, llvm::SelectionDAG::makeEquivalentMemoryOrdering(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and SDValue().

◆ combineBVOfVecSExt()

SDValue combineBVOfVecSExt	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 16528 of file PPCISelLowering.cpp.

References addShuffleForVecExtend(), llvm::ISD::ANY_EXTEND, llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::DataLayout::isLittleEndian(), N, SDValue(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::SIGN_EXTEND_INREG.

◆ combineBVZEXTLOAD()

SDValue combineBVZEXTLOAD	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 16626 of file PPCISelLowering.cpp.

References llvm::cast(), DL, llvm::ISD::EXTLOAD, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getOpcode(), llvm::SelectionDAG::getVTList(), llvm::ISD::LOAD, N, SDValue(), and llvm::ISD::ZEXTLOAD.

◆ combineSELECT_CCBitFloor()

SDValue combineSELECT_CCBitFloor	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Optimize the bitfloor(X) pattern for PowerPC.

Transforms: select_cc X, 0, 0, (srl MinSignedValue, (ctlz X)), seteq Into: srl MinSignedValue, (ctlz X)

This is safe on PowerPC because the srw instruction returns 0 when the shift amount is == bitwidth, which matches the behavior we need for X=0.

Definition at line 17480 of file PPCISelLowering.cpp.

References llvm::cast(), llvm::ISD::CTLZ, DL, llvm::dyn_cast(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::isNullConstant(), N, SDValue(), llvm::ISD::SELECT_CC, llvm::ISD::SETEQ, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ combineXorSelectCC()

SDValue combineXorSelectCC	(	SDNode *	N,
		SelectionDAG &	DAG )

static

◆ combineZextSetccWithZero()

SDValue combineZextSetccWithZero	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 17572 of file PPCISelLowering.cpp.

References llvm::cast(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isNullConstant(), LHS, N, RHS, SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETNE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ computeFlagsForAddressComputation()

void computeFlagsForAddressComputation	(	SDValue	N,
		unsigned &	FlagSet,
		SelectionDAG &	DAG )

static

Given a node, compute flags that are used for address computation when selecting load and store instructions.

The flags computed are stored in FlagSet. This function takes into account whether the node is a constant, an ADD, OR, or a constant, and computes the address flags accordingly.

Definition at line 20347 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::dyn_cast(), llvm::APInt::getZExtValue(), llvm::APInt::isSignedIntN(), llvm::PPC::MOF_AddrIsSImm32, llvm::PPC::MOF_NotAddNorCst, llvm::PPC::MOF_RPlusLo, llvm::PPC::MOF_RPlusR, llvm::PPC::MOF_RPlusSImm16, llvm::PPC::MOF_RPlusSImm16Mult16, llvm::PPC::MOF_RPlusSImm16Mult4, llvm::PPC::MOF_RPlusSImm34, N, provablyDisjointOr(), RHS, and setAlignFlagsForFI().

◆ ConvertCarryFlagToCarryValue()

SDValue ConvertCarryFlagToCarryValue	(	EVT	SumType,
		SDValue	Flag,
		EVT	CarryType,
		SelectionDAG &	DAG,
		const PPCSubtarget &	STI )

static

Definition at line 12644 of file PPCISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), and llvm::ISD::SETNE.

◆ ConvertCarryValueToCarryFlag()

SDValue ConvertCarryValueToCarryFlag	(	EVT	SumType,
		SDValue	Value,
		SelectionDAG &	DAG,
		const PPCSubtarget &	STI )

static

Definition at line 12629 of file PPCISelLowering.cpp.

References DL, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), and llvm::ISD::SELECT.

◆ convertFPToInt()

SDValue convertFPToInt	(	SDValue	Op,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget )

static

Definition at line 8347 of file PPCISelLowering.cpp.

References assert(), llvm::ISD::DELETED_NODE, llvm::ISD::FP_EXTEND, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getNode(), getPPCStrictOpcode(), llvm::PPCSubtarget::getScalarIntVT(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm_unreachable, Opc, SDValue(), llvm::SDNodeFlags::setNoFPExcept(), llvm::MVT::SimpleTy, llvm::ISD::STRICT_FP_EXTEND, and llvm::ISD::STRICT_FP_TO_SINT.

◆ convertIntToFP()

SDValue convertIntToFP	(	SDValue	Op,
		SDValue	Src,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget,
		SDValue	Chain = SDValue() )

static

Definition at line 8654 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getNode(), getPPCStrictOpcode(), llvm::SelectionDAG::getVTList(), llvm::SDNodeFlags::setNoFPExcept(), llvm::ISD::SINT_TO_FP, and llvm::ISD::STRICT_SINT_TO_FP.

◆ ConvertSETCCToXori()

SDValue ConvertSETCCToXori	(	SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 16009 of file PPCISelLowering.cpp.

References llvm::ISD::AND, assert(), llvm::cast(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), LHS, llvm_unreachable, N, RHS, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::TRUNCATE, llvm::ISD::XOR, and llvm::Xor.

◆ convertTwoLoadsAndCmpToVCMPEQUB()

SDValue convertTwoLoadsAndCmpToVCMPEQUB	(	SelectionDAG &	DAG,
		SDNode *	N,
		const SDLoc &	DL )

Definition at line 15888 of file PPCISelLowering.cpp.

References assert(), llvm::cast(), llvm::ISD::Constant, DL, llvm::MachineMemOperand::getAAInfo(), llvm::MachineMemOperand::getAlign(), llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::MachineMemOperand::getFailureOrdering(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getMachineMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::MachineMemOperand::getPointerInfo(), llvm::SelectionDAG::getSetCC(), llvm::MachineMemOperand::getSize(), llvm::MachineMemOperand::getSuccessOrdering(), llvm::MachineMemOperand::getSyncScopeID(), llvm::SDValue::getValue(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::LOAD, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), SDValue(), llvm::ISD::SETCC, llvm::ISD::SETEQ, and llvm::ISD::SETNE.

◆ createAtomicLoopBlocks()

void createAtomicLoopBlocks	(	MachineFunction *	F,
		MachineBasicBlock *	BB,
		MachineBasicBlock *&	loop1MBB,
		MachineBasicBlock *&	loop2MBB,
		MachineBasicBlock *&	exitMBB,
		MachineInstr &	MI,
		MachineFunction::iterator	It )

static

Helper function to create basic blocks for atomic compare-and-swap.

Creates three basic blocks (loop1MBB, loop2MBB, exitMBB) and sets up the control flow structure common to both hardware and software implementations of atomic compare-and-swap operations.

Definition at line 14098 of file PPCISelLowering.cpp.

References llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), F, llvm::MachineBasicBlock::getBasicBlock(), MI, llvm::MachineBasicBlock::splice(), and llvm::MachineBasicBlock::transferSuccessorsAndUpdatePHIs().

Referenced by emitAtomicCmpSwapHardware(), and emitAtomicCmpSwapSoftware().

◆ CreateCopyOfByValArgument()

SDValue CreateCopyOfByValArgument	(	SDValue	Src,
		SDValue	Dst,
		SDValue	Chain,
		ISD::ArgFlagsTy	Flags,
		SelectionDAG &	DAG,
		const SDLoc &	dl )

static

CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst" of size "Size".

Alignment information is specified by the specific parameter attribute. The copy will be passed as a byval function parameter. Sometimes what we are copying is the end of a larger object, the part that does not fit in registers.

Definition at line 5199 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getConstant(), and llvm::SelectionDAG::getMemcpy().

◆ DAGCombineAddc()

SDValue DAGCombineAddc	(	SDNode *	N,
		llvm::PPCTargetLowering::DAGCombinerInfo &	DCI )

static

Definition at line 17459 of file PPCISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::isAllOnesConstant(), llvm::isNullConstant(), LHS, N, RHS, and SDValue().

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ emitAtomicCmpSwapHardware()

MachineBasicBlock * emitAtomicCmpSwapHardware	(	MachineInstr &	MI,
		MachineBasicBlock *	BB,
		const TargetInstrInfo *	TII,
		const PPCSubtarget &	Subtarget )

static

Emit hardware-supported atomic compare-and-swap for I32/I64 and I8/I16 with partword atomic support.

This uses native PowerPC atomic instructions (LBARX/LHARX/LWARX/LDARX for load-and-reserve, STBCX/STHCX/STWCX/STDCX for store-conditional) to implement atomic compare-and-swap at byte, halfword, word, or doubleword granularity.

Control flow: thisMBB -> loop1MBB -> loop2MBB -> exitMBB | | +---------—+

loop1MBB:

Load-and-reserve from memory
Compare loaded value with expected old value
Branch to exitMBB if not equal (CAS failed) loop2MBB:
Store-conditional new value to memory
Branch back to loop1MBB if store failed (retry)
Fall through to exitMBB on success

Definition at line 14139 of file PPCISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), assert(), llvm::BuildMI(), createAtomicLoopBlocks(), F, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm_unreachable, MI, llvm::PPC::PRED_NE_MINUS, and TII.

Referenced by llvm::PPCTargetLowering::EmitInstrWithCustomInserter().

◆ emitAtomicCmpSwapSoftware()

MachineBasicBlock * emitAtomicCmpSwapSoftware	(	MachineInstr &	MI,
		MachineBasicBlock *	BB,
		const TargetInstrInfo *	TII,
		const PPCSubtarget &	Subtarget )

static

Emit software-emulated atomic compare-and-swap for I8/I16 without hardware partword atomic support.

This emulates byte/halfword atomic operations using word (32-bit) atomic instructions. Since PowerPC atomic instructions work at word granularity, we must:

Align the pointer to a word boundary
Calculate the bit shift for the target byte/halfword within the word
Create masks to isolate the target byte/halfword
Shift old/new values into the correct bit position
Use LWARX/STWCX on the full word
Mask and merge to preserve other bytes in the word
Extract and shift the result back

Control flow: thisMBB -> loop1MBB -> loop2MBB -> exitMBB | | +---------—+

loop1MBB:

LWARX: Load-and-reserve full word
Mask to extract target byte/halfword
Compare with expected old value
Branch to exitMBB if not equal (CAS failed) loop2MBB:
Merge new value with other bytes in the word
STWCX: Store-conditional full word
Branch back to loop1MBB if store failed (retry)
Fall through to exitMBB on success exitMBB:
Extract and return the loaded value

Definition at line 14253 of file PPCISelLowering.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), createAtomicLoopBlocks(), F, llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineBasicBlock::getParent(), llvm::PPCSubtarget::isLittleEndian(), MI, llvm::PPC::PRED_NE, and TII.

Referenced by llvm::PPCTargetLowering::EmitInstrWithCustomInserter().

◆ emitSelect()

MachineBasicBlock * emitSelect	(	MachineInstr &	MI,
		MachineBasicBlock *	BB,
		const TargetInstrInfo *	TII,
		const PPCSubtarget &	Subtarget )

static

Emit SELECT instruction, using ISEL if available, otherwise use branch-based control flow.

For targets with ISEL support (SELECT_CC_I4/I8, SELECT_I4/I8), this generates a single ISEL instruction. Otherwise, it creates a branch-based control flow pattern with PHI nodes.

Definition at line 14012 of file PPCISelLowering.cpp.

Referenced by llvm::PPCTargetLowering::EmitInstrWithCustomInserter().

◆ EmitTailCallStoreFPAndRetAddr()

SDValue EmitTailCallStoreFPAndRetAddr	(	SelectionDAG &	DAG,
		SDValue	Chain,
		SDValue	OldRetAddr,
		SDValue	OldFP,
		int	SPDiff,
		const SDLoc &	dl )

static

EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack slot for the tail call optimized function call.

Definition at line 5139 of file PPCISelLowering.cpp.

References llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::PPCSubtarget::getFrameLowering(), llvm::SelectionDAG::getMachineFunction(), llvm::PPCSubtarget::getScalarIntVT(), llvm::SelectionDAG::getStore(), and llvm::MachineFunction::getSubtarget().

Referenced by PrepareTailCall().

◆ EnsureStackAlignment()

unsigned EnsureStackAlignment	(	const PPCFrameLowering *	Lowering,
		unsigned	NumBytes )

static

EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required for target.

Definition at line 4137 of file PPCISelLowering.cpp.

References llvm::alignTo(), and Lowering.

◆ findConsecutiveLoad()

bool findConsecutiveLoad	(	LoadSDNode *	LD,
		SelectionDAG &	DAG )

static

Definition at line 15142 of file PPCISelLowering.cpp.

References llvm::cast(), llvm::SmallPtrSetImplBase::clear(), llvm::SmallPtrSetImpl< PtrType >::count(), llvm::dyn_cast(), getNode(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::EVT::getStoreSize(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::isa(), isConsecutiveLS(), llvm::SDNode::ops(), llvm::ISD::TokenFactor, and llvm::SDNode::users().

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ fixupFuncForFI()

void fixupFuncForFI	(	SelectionDAG &	DAG,
		int	FrameIdx,
		EVT	VT )

static

Definition at line 2642 of file PPCISelLowering.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFrameInfo::getObjectAlign(), and llvm::PPCFunctionInfo::setHasNonRISpills().

Referenced by llvm::PPCTargetLowering::SelectAddressRegImm(), and llvm::PPCTargetLowering::SelectOptimalAddrMode().

◆ fixupShuffleMaskForPermutedSToV()

void fixupShuffleMaskForPermutedSToV	(	SmallVectorImpl< int > &	ShuffV,
		int	LHSFirstElt,
		int	LHSLastElt,
		int	RHSFirstElt,
		int	RHSLastElt,
		int	HalfVec,
		unsigned	LHSNumValidElts,
		unsigned	RHSNumValidElts,
		const PPCSubtarget &	Subtarget )

static

Definition at line 17091 of file PPCISelLowering.cpp.

References E(), I, llvm::PPCSubtarget::isLittleEndian(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

◆ generateEquivalentSub()

SDValue generateEquivalentSub	(	SDNode *	N,
		int	Size,
		bool	Complement,
		bool	Swap,
		SDLoc &	DL,
		SelectionDAG &	DAG )

static

This function is called when we have proved that a SETCC node can be replaced by subtraction (and other supporting instructions) so that the result of comparison is kept in a GPR instead of CR.

This function is purely for codegen purposes and has some flags to guide the codegen process.

Definition at line 15208 of file PPCISelLowering.cpp.

References assert(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), N, llvm::ISD::SETCC, Size, llvm::ISD::SRL, llvm::ISD::SUB, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::XOR, and llvm::ISD::ZERO_EXTEND.

◆ GeneratePerfectShuffle()

SDValue GeneratePerfectShuffle	(	unsigned	PFEntry,
		SDValue	LHS,
		SDValue	RHS,
		SelectionDAG &	DAG,
		const SDLoc &	dl )

static

GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.

Definition at line 9982 of file PPCISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, BuildVSLDOI(), GeneratePerfectShuffle(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), LHS, llvm_unreachable, OP_COPY, llvm::PerfectShuffleTable, RHS, and T.

◆ generateSToVPermutedForVecShuffle()

SDValue generateSToVPermutedForVecShuffle	(	int	ScalarSize,
		uint64_t	ShuffleEltWidth,
		unsigned &	NumValidElts,
		int	FirstElt,
		int &	LastElt,
		SDValue	VecShuffOperand,
		SDValue	SToVNode,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget )

static

Definition at line 17161 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getBitcast(), llvm::EVT::getScalarSizeInBits(), getSToVPermuted(), and llvm::SDValue::getValueType().

◆ getBaseWithConstantOffset()

void getBaseWithConstantOffset	(	SDValue	Loc,
		SDValue &	Base,
		int64_t &	Offset,
		SelectionDAG &	DAG )

static

Definition at line 15013 of file PPCISelLowering.cpp.

References llvm::sampleprof::Base, llvm::cast(), getBaseWithConstantOffset(), llvm::SelectionDAG::isBaseWithConstantOffset(), and llvm::Offset.

◆ getCallOpcode()

unsigned getCallOpcode	(	PPCTargetLowering::CallFlags	CFlags,
		const Function &	Caller,
		const SDValue &	Callee,
		const PPCSubtarget &	Subtarget,
		const TargetMachine &	TM,
		bool	IsStrictFPCall = false )

static

Definition at line 5364 of file PPCISelLowering.cpp.

References assert(), callsShareTOCBase(), llvm::dyn_cast(), G, llvm::PPCSubtarget::is64BitELFABI(), llvm::PPCSubtarget::isAIXABI(), llvm::PPCTargetLowering::CallFlags::IsIndirect, llvm::PPCTargetLowering::CallFlags::IsTailCall, isTOCSaveRestoreRequired(), llvm::PPCSubtarget::isUsingPCRelativeCalls(), and llvm_unreachable.

◆ getCanonicalConstSplat()

SDValue getCanonicalConstSplat	(	uint64_t	Val,
		unsigned	SplatSize,
		EVT	VT,
		SelectionDAG &	DAG,
		const SDLoc &	dl )

static

getCanonicalConstSplat - Build a canonical splat immediate of Val with an element size of SplatSize.

Cast the result to VT.

Definition at line 9334 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getBitcast(), and llvm::SelectionDAG::getConstant().

◆ getDataClassTest()

SDValue getDataClassTest	(	SDValue	Op,
		FPClassTest	Mask,
		const SDLoc &	Dl,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget )

static

Definition at line 11787 of file PPCISelLowering.cpp.

Referenced by getDataClassTest().

◆ getEstimateRefinementSteps()

int getEstimateRefinementSteps	(	EVT	VT,
		const PPCSubtarget &	Subtarget )

static

Definition at line 14900 of file PPCISelLowering.cpp.

References llvm::EVT::getScalarType().

◆ getIntrinsicForAtomicRMWBinOp128()

Intrinsic::ID getIntrinsicForAtomicRMWBinOp128 ( AtomicRMWInst::BinOp BinOp )

static

Definition at line 20882 of file PPCISelLowering.cpp.

References llvm::AtomicRMWInst::Add, llvm::AtomicRMWInst::And, llvm_unreachable, llvm::AtomicRMWInst::Nand, llvm::AtomicRMWInst::Or, llvm::AtomicRMWInst::Sub, llvm::AtomicRMWInst::Xchg, and llvm::AtomicRMWInst::Xor.

Referenced by llvm::PPCTargetLowering::emitMaskedAtomicRMWIntrinsic().

◆ getLabelAccessInfo()

void getLabelAccessInfo	(	bool	IsPIC,
		const PPCSubtarget &	Subtarget,
		unsigned &	HiOpFlags,
		unsigned &	LoOpFlags,
		const GlobalValue *	GV = nullptr )

static

Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.

Definition at line 3015 of file PPCISelLowering.cpp.

References llvm::PPCII::MO_HA, llvm::PPCII::MO_LO, llvm::PPCII::MO_PIC_HA_FLAG, and llvm::PPCII::MO_PIC_LO_FLAG.

◆ getMaxByValAlign()

void getMaxByValAlign	(	Type *	Ty,
		Align &	MaxAlign,
		Align	MaxMaxAlign )

static

getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment.

Definition at line 1648 of file PPCISelLowering.cpp.

References llvm::dyn_cast(), and getMaxByValAlign().

Referenced by llvm::PPCTargetLowering::getByValTypeAlignment(), llvm::X86TargetLowering::getByValTypeAlignment(), getMaxByValAlign(), and getMaxByValAlign().

◆ getNormalLoadInput()

const SDValue * getNormalLoadInput	(	const SDValue &	Op,
		bool &	IsPermuted )

static

Definition at line 9476 of file PPCISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::cast(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isNormalLoad(), llvm::ISD::LOAD, and llvm::ISD::SCALAR_TO_VECTOR.

◆ getOutputChainFromCallSeq()

SDValue getOutputChainFromCallSeq ( SDValue CallSeqStart )

static

Definition at line 5511 of file PPCISelLowering.cpp.

References assert(), llvm::ISD::CALLSEQ_START, llvm::SDNode::getNumValues(), llvm::SDValue::getOpcode(), llvm::SDValue::getValue(), and llvm::SDValue::getValueType().

Referenced by prepareDescriptorIndirectCall().

◆ getPatternInfo()

std::optional< LXVKQPattern > getPatternInfo ( const APInt & FullVal )

static

Definition at line 16258 of file PPCISelLowering.cpp.

◆ getPPCStrictOpcode()

unsigned getPPCStrictOpcode ( unsigned Opc )

static

Definition at line 8324 of file PPCISelLowering.cpp.

References llvm_unreachable, and Opc.

Referenced by convertFPToInt(), and convertIntToFP().

◆ getRegClassForSVT()

const TargetRegisterClass * getRegClassForSVT	(	MVT::SimpleValueType	SVT,
		bool	IsPPC64,
		bool	HasP8Vector,
		bool	HasVSX )

static

Definition at line 7043 of file PPCISelLowering.cpp.

References assert(), and llvm::report_fatal_error().

◆ getSToVPermuted()

SDValue getSToVPermuted	(	SDValue	OrigSToV,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget )

static

Definition at line 17113 of file PPCISelLowering.cpp.

References assert(), llvm::dyn_cast(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::ConstantSDNode::getZExtValue(), llvm::PPCSubtarget::isLittleEndian(), and llvm::ISD::SCALAR_TO_VECTOR.

Referenced by generateSToVPermutedForVecShuffle().

◆ getVectorCompareInfo()

bool getVectorCompareInfo	(	SDValue	Intrin,
		int &	CompareOpc,
		bool &	isDot,
		const PPCSubtarget &	Subtarget )

static

getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison.

If it is, return true and fill in Opc/isDot with information about the intrinsic.

Definition at line 10807 of file PPCISelLowering.cpp.

References llvm::SDValue::getConstantOperandVal(), and llvm_unreachable.

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ hasSameArgumentList()

bool hasSameArgumentList	(	const Function *	CallerFn,
		const CallBase &	CB )

static

Definition at line 4927 of file PPCISelLowering.cpp.

References llvm::CallBase::arg_begin(), llvm::Function::arg_begin(), llvm::CallBase::arg_end(), llvm::CallBase::arg_size(), llvm::Function::arg_size(), llvm::Value::getType(), and llvm::isa().

◆ haveEfficientBuildVectorPattern()

bool haveEfficientBuildVectorPattern	(	BuildVectorSDNode *	V,
		bool	HasDirectMove,
		bool	HasP8Vector )

static

Do we have an efficient pattern in a .td file for this node?

Parameters

V	- pointer to the BuildVectorSDNode being matched
HasDirectMove	- does this subtarget have VSR <-> GPR direct moves?

There are some patterns where it is beneficial to keep a BUILD_VECTOR node as a BUILD_VECTOR node rather than expanding it. The patterns where the opposite is true (expansion is beneficial) are:

The node builds a vector out of integers that are not 32 or 64-bits
The node builds a vector out of constants
The node is a "load-and-splat" In all other cases, we will choose to keep the BUILD_VECTOR.

Definition at line 9414 of file PPCISelLowering.cpp.

References llvm::ISD::FP_ROUND, llvm::ISD::FP_TO_SINT, llvm::ISD::FP_TO_UINT, llvm::SDNode::getOperand(), and llvm::ISD::LOAD.

◆ invertFMAOpcode()

unsigned invertFMAOpcode ( unsigned Opc )

static

Definition at line 19599 of file PPCISelLowering.cpp.

References llvm::ISD::FMA, llvm_unreachable, and Opc.

◆ isAlternatingShuffMask()

bool isAlternatingShuffMask	(	const ArrayRef< int > &	Mask,
		int	NumElts )

static

Definition at line 17039 of file PPCISelLowering.cpp.

◆ isBLACompatibleAddress()

SDNode * isBLACompatibleAddress	(	SDValue	Op,
		SelectionDAG &	DAG )

static

isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable in the immediate field of a BxA instruction.

Definition at line 5093 of file PPCISelLowering.cpp.

References llvm::CallingConv::C, llvm::dyn_cast(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getSignedConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::SignExtend32().

Referenced by isIndirectCall(), and transformCallee().

◆ isConsecutiveLS()

bool isConsecutiveLS	(	SDNode *	N,
		LSBaseSDNode *	Base,
		unsigned	Bytes,
		int	Dist,
		SelectionDAG &	DAG )

static

Definition at line 15065 of file PPCISelLowering.cpp.

References llvm::sampleprof::Base, llvm::dyn_cast(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, isConsecutiveLSLoc(), and N.

Referenced by findConsecutiveLoad().

◆ isConsecutiveLSLoc()

bool isConsecutiveLSLoc	(	SDValue	Loc,
		EVT	VT,
		LSBaseSDNode *	Base,
		unsigned	Bytes,
		int	Dist,
		SelectionDAG &	DAG )

static

Definition at line 15025 of file PPCISelLowering.cpp.

References llvm::sampleprof::Base, llvm::cast(), llvm::ISD::FrameIndex, getBaseWithConstantOffset(), llvm::MachineFunction::getFrameInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SDValue::getNode(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::TargetLowering::isGAPlusOffset().

Referenced by isConsecutiveLS().

◆ isConstantOrUndef()

bool isConstantOrUndef	(	int	Op,
		int	Val )

static

isConstantOrUndef - Op is either an undef node or a ConstantSDNode.

Return true if Op is undef or if it matches the specified value.

Definition at line 1752 of file PPCISelLowering.cpp.

◆ isFloatingPointZero()

bool isFloatingPointZero ( SDValue Op )

static

isFloatingPointZero - Return true if this is 0.0 or -0.0.

Definition at line 1738 of file PPCISelLowering.cpp.

References llvm::dyn_cast(), llvm::ISD::isEXTLoad(), and llvm::ISD::isNON_EXTLoad().

◆ isFPExtLoad()

bool isFPExtLoad ( SDValue Op )

static

Definition at line 16154 of file PPCISelLowering.cpp.

References llvm::dyn_cast(), and llvm::ISD::EXTLOAD.

◆ isFunctionGlobalAddress()

bool isFunctionGlobalAddress ( const GlobalValue * CalleeGV )

static

Definition at line 5259 of file PPCISelLowering.cpp.

References llvm::GlobalValue::getValueType(), llvm::Type::isFunctionTy(), and llvm::GlobalValue::isThreadLocal().

Referenced by isIndirectCall(), and transformCallee().

◆ isGPRShadowAligned()

bool isGPRShadowAligned	(	MCPhysReg	Reg,
		Align	RequiredAlign )

static

Definition at line 6766 of file PPCISelLowering.cpp.

References assert(), Reg, llvm::report_fatal_error(), and llvm::Align::value().

Referenced by CC_AIX().

◆ isIndirectCall()

bool isIndirectCall	(	const SDValue &	Callee,
		SelectionDAG &	DAG,
		const PPCSubtarget &	Subtarget,
		bool	isPatchPoint )

static

Definition at line 5334 of file PPCISelLowering.cpp.

References llvm::dyn_cast(), G, llvm::isa(), isBLACompatibleAddress(), llvm::PPCSubtarget::isELFv2ABI(), isFunctionGlobalAddress(), and llvm::PPCSubtarget::usesFunctionDescriptors().

◆ isNByteElemShuffleMask()

bool isNByteElemShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	Width,
		int	StepLen )

static

Check that the mask is shuffling N byte elements.

Within each N byte element of the mask, the indices could be either in increasing or decreasing order as long as they are consecutive.

Parameters

[in]	N	the shuffle vector SD Node to analyze
[in]	Width	the element width in bytes, could be 2/4/8/16 (HalfWord/ Word/DoubleWord/QuadWord).
[in]	StepLen	the delta indices number among the N byte element, if the mask is in increasing/decreasing order then it is 1/-1.

Returns: true iff the mask is shuffling N byte elements.

Definition at line 2135 of file PPCISelLowering.cpp.

References assert(), and N.

Referenced by isXXBRShuffleMaskHelper(), llvm::PPC::isXXINSERTWMask(), llvm::PPC::isXXPERMDIShuffleMask(), and llvm::PPC::isXXSLDWIShuffleMask().

◆ isPCRelNode()

bool isPCRelNode ( SDValue N )

static

Definition at line 20399 of file PPCISelLowering.cpp.

References isValidPCRelNode(), and N.

Referenced by llvm::PPCTargetLowering::SelectOptimalAddrMode().

◆ isScalarToVec()

SDValue isScalarToVec ( SDValue Op )

static

Definition at line 17072 of file PPCISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::SCALAR_TO_VECTOR, and SDValue().

◆ IsSelect()

bool IsSelect	(	unsigned	Opcode,
		bool	CheckOnlyCC = false )

static

Check if the opcode is a SELECT or SELECT_CC variant.

Parameters

Opcode	The opcode to check
CheckOnlyCC	If true, only return true for SELECT_CC variants; if false, return true for both SELECT and SELECT_CC

Definition at line 13972 of file PPCISelLowering.cpp.

Referenced by llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), emitSelect(), llvm::InstCombiner::getFreelyInvertedImpl(), isReductionCandidate(), and IsSelectCC().

◆ IsSelectCC()

bool IsSelectCC ( unsigned Opcode )

static

Definition at line 14004 of file PPCISelLowering.cpp.

References IsSelect().

Referenced by emitSelect().

◆ isShuffleMaskInRange()

bool isShuffleMaskInRange	(	const SmallVectorImpl< int > &	ShuffV,
		int	HalfVec,
		int	LHSLastElementDefined,
		int	RHSLastElementDefined )

static

Definition at line 17143 of file PPCISelLowering.cpp.

◆ isSignExtended()

bool isSignExtended	(	MachineInstr &	MI,
		const PPCInstrInfo *	TII )

static

Definition at line 13250 of file PPCISelLowering.cpp.

References MI, and TII.

◆ isSplatBV()

bool isSplatBV ( SDValue Op )

static

Definition at line 17053 of file PPCISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, and llvm::SDValue::isUndef().

◆ isStoreConditional()

bool isStoreConditional	(	SDValue	Intrin,
		unsigned &	StoreWidth )

static

Definition at line 17444 of file PPCISelLowering.cpp.

References llvm::SDValue::getConstantOperandVal().

Referenced by llvm::PPCTargetLowering::PerformDAGCombine().

◆ isTOCSaveRestoreRequired()

bool isTOCSaveRestoreRequired ( const PPCSubtarget & Subtarget )

inlinestatic

Definition at line 5359 of file PPCISelLowering.cpp.

References llvm::PPCSubtarget::is64BitELFABI(), llvm::PPCSubtarget::isAIXABI(), and llvm::PPCSubtarget::isUsingPCRelativeCalls().

Referenced by buildCallOperands(), and getCallOpcode().

◆ isValidMtVsrBmi()

bool isValidMtVsrBmi	(	APInt &	BitMask,
		BuildVectorSDNode &	BVN,
		bool	IsLittleEndian )

Definition at line 9567 of file PPCISelLowering.cpp.

References assert(), llvm::APInt::clearAllBits(), llvm::dyn_cast(), llvm::APInt::extractBits(), llvm::SDNode::getNumOperands(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::APInt::insertBits(), llvm::SDNode::op_values(), and llvm::APInt::setBit().

◆ isValidPCRelNode()

template<typename Ty>

bool isValidPCRelNode ( SDValue N )

static

Definition at line 2861 of file PPCISelLowering.cpp.

References llvm::dyn_cast(), llvm::PPCInstrInfo::hasPCRelFlag(), and N.

Referenced by isPCRelNode(), and llvm::PPCTargetLowering::SelectAddressPCRel().

◆ isValidSplatLoad()

bool isValidSplatLoad	(	const PPCSubtarget &	Subtarget,
		const SDValue &	Op,
		unsigned &	Opcode )

static

Definition at line 9531 of file PPCISelLowering.cpp.

References llvm::dyn_cast(), llvm::MemSDNode::getMemoryVT(), llvm::EVT::getVectorElementType(), llvm::ISD::isEXTLoad(), llvm::ISD::isNON_EXTLoad(), llvm::ISD::isSEXTLoad(), llvm::ISD::isUNINDEXEDLoad(), and llvm::ISD::isZEXTLoad().

◆ isVMerge() [1/2]

bool isVMerge	(	ShuffleVectorSDNode *	N,
		unsigned	IndexOffset,
		unsigned	RHSStartValue )

static

Common function used to match vmrgew and vmrgow shuffles.

The indexOffset determines whether to look for even or odd words in the shuffle mask. This is based on the of the endianness of the target machine.

Little Endian:
- Use offset of 0 to check for odd elements
- Use offset of 4 to check for even elements
Big Endian:
- Use offset of 0 to check for even elements
- Use offset of 4 to check for odd elements A detailed description of the vector element ordering for little endian and big endian can be found at http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html Targeting your applications - what little endian and big endian IBM XL C/C++ compiler differences mean to you

The mask to the shuffle vector instruction specifies the indices of the elements from the two input vectors to place in the result. The elements are numbered in array-access order, starting with the first vector. These vectors are always of type v16i8, thus each vector will contain 16 elements of size

More info on the shuffle vector can be found in the http://llvm.org/docs/LangRef.html#shufflevector-instruction Language Reference.

The RHSStartValue indicates whether the same input vectors are used (unary) or two different input vectors are used, based on the following:

If the instruction uses the same vector for both inputs, the range of the indices will be 0 to 15. In this case, the RHSStart value passed should be 0.
If the instruction has two different vectors then the range of the indices will be 0 to 31. In this case, the RHSStart value passed should be 16 (indices 0-15 specify elements in the first vector while indices 16 to 31 specify elements in the second vector).

Parameters

[in]	N	The shuffle vector SD Node to analyze
[in]	IndexOffset	Specifies whether to look for even or odd elements
[in]	RHSStartValue	Specifies the starting index for the righthand input vector to the shuffle_vector instruction

Returns: true iff this shuffle vector represents an even or odd word merge

Definition at line 1983 of file PPCISelLowering.cpp.

References isConstantOrUndef(), and N.

◆ isVMerge() [2/2]

bool isVMerge	(	ShuffleVectorSDNode *	N,
		unsigned	UnitSize,
		unsigned	LHSStart,
		unsigned	RHSStart )

static

isVMerge - Common function, used to match vmrg* shuffles.

Definition at line 1873 of file PPCISelLowering.cpp.

References assert(), isConstantOrUndef(), and N.

Referenced by llvm::PPC::isVMRGEOShuffleMask(), llvm::PPC::isVMRGHShuffleMask(), and llvm::PPC::isVMRGLShuffleMask().

◆ isXXBRShuffleMaskHelper()

bool isXXBRShuffleMaskHelper	(	ShuffleVectorSDNode *	N,
		int	Width )

static

Definition at line 2299 of file PPCISelLowering.cpp.

References assert(), isNByteElemShuffleMask(), and N.

Referenced by llvm::PPC::isXXBRDShuffleMask(), llvm::PPC::isXXBRHShuffleMask(), llvm::PPC::isXXBRQShuffleMask(), and llvm::PPC::isXXBRWShuffleMask().

◆ LowerLabelRef()

SDValue LowerLabelRef	(	SDValue	HiPart,
		SDValue	LoPart,
		bool	isPIC,
		SelectionDAG &	DAG )

static

Definition at line 3028 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::PPCISD::GlobalBaseReg, llvm::Hi, and llvm::Lo.

◆ LowerMemOpCallTo()

void LowerMemOpCallTo	(	SelectionDAG &	DAG,
		MachineFunction &	MF,
		SDValue	Chain,
		SDValue	Arg,
		SDValue	PtrOff,
		int	SPDiff,
		unsigned	ArgOffset,
		bool	isPPC64,
		bool	isTailCall,
		bool	isVector,
		SmallVectorImpl< SDValue > &	MemOpChains,
		SmallVectorImpl< TailCallArgumentInfo > &	TailCallArguments,
		const SDLoc &	dl )

static

LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls.

Definition at line 5210 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, CalculateTailCallArgDest(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ mapArgRegToOffsetAIX()

unsigned mapArgRegToOffsetAIX	(	unsigned	Reg,
		const PPCFrameLowering *	FL )

static

Definition at line 7088 of file PPCISelLowering.cpp.

References assert(), contains(), llvm::PPCFrameLowering::getLinkageSize(), llvm_unreachable, and Reg.

◆ needStackSlotPassParameters()

bool needStackSlotPassParameters	(	const PPCSubtarget &	Subtarget,
		const SmallVectorImpl< ISD::OutputArg > &	Outs )

static

Definition at line 4891 of file PPCISelLowering.cpp.

References assert(), CalculateStackSlotUsed(), llvm::PPCSubtarget::getFrameLowering(), llvm::PPCFrameLowering::getLinkageSize(), and llvm::PPCSubtarget::is64BitELFABI().

◆ prepareDescriptorIndirectCall()

void prepareDescriptorIndirectCall	(	SelectionDAG &	DAG,
		SDValue &	Callee,
		SDValue &	Glue,
		SDValue &	Chain,
		SDValue	CallSeqStart,
		const CallBase *	CB,
		const SDLoc &	dl,
		bool	hasNest,
		const PPCSubtarget &	Subtarget )

static

◆ prepareIndirectCall()

void prepareIndirectCall	(	SelectionDAG &	DAG,
		SDValue &	Callee,
		SDValue &	Glue,
		SDValue &	Chain,
		const SDLoc &	dl )

static

Definition at line 5527 of file PPCISelLowering.cpp.

References llvm::ArrayRef(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), and llvm::SDValue::getValue().

Referenced by prepareDescriptorIndirectCall().

◆ prepareOutOfLineGlueCall()

void prepareOutOfLineGlueCall	(	SelectionDAG &	DAG,
		SDValue &	Callee,
		SDValue &	Glue,
		SDValue &	Chain,
		SDValue	CallSeqStart,
		const CallBase *	CB,
		const SDLoc &	dl,
		bool	hasNest,
		const PPCSubtarget &	Subtarget )

static

Definition at line 5630 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getCopyToReg(), llvm::PPCSubtarget::getGlueCodeDescriptorRegister(), and llvm::SDValue::getValue().

◆ PrepareTailCall()

void PrepareTailCall	(	SelectionDAG &	DAG,
		SDValue &	InGlue,
		SDValue &	Chain,
		const SDLoc &	dl,
		int	SPDiff,
		unsigned	NumBytes,
		SDValue	LROp,
		SDValue	FPOp,
		SmallVectorImpl< TailCallArgumentInfo > &	TailCallArguments )

static

Definition at line 5235 of file PPCISelLowering.cpp.

References EmitTailCallStoreFPAndRetAddr(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), SDValue(), StoreTailCallArgumentsToStackSlot(), and llvm::ISD::TokenFactor.

◆ provablyDisjointOr()

bool provablyDisjointOr	(	SelectionDAG &	DAG,
		const SDValue &	N )

static

Used when computing address flags for selecting loads and stores.

If we have an OR, check if the LHS and RHS are provably disjoint. An OR of two provably disjoint values is equivalent to an ADD. Most PPC load/store instructions compute the effective address as a sum, so doing this conversion is useful.

Definition at line 2539 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::computeKnownBits(), llvm::APInt::getBoolValue(), N, llvm::ISD::OR, and llvm::KnownBits::Zero.

Referenced by computeFlagsForAddressComputation(), and llvm::PPCTargetLowering::SelectForceXFormMode().

◆ setAlignFlagsForFI()

void setAlignFlagsForFI	(	SDValue	N,
		unsigned &	FlagSet,
		SelectionDAG &	DAG )

static

Set alignment flags based on whether or not the Frame Index is aligned.

Utilized when computing flags for address computation when selecting load and store instructions.

Definition at line 20318 of file PPCISelLowering.cpp.

References llvm::ISD::ADD, llvm::dyn_cast(), llvm::MachineFunction::getFrameInfo(), llvm::FrameIndexSDNode::getIndex(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFrameInfo::getObjectAlign(), llvm::PPC::MOF_RPlusSImm16Mult16, llvm::PPC::MOF_RPlusSImm16Mult4, N, llvm::ISD::OR, and llvm::Align::value().

Referenced by computeFlagsForAddressComputation().

◆ setUsesTOCBasePtr() [1/2]

void setUsesTOCBasePtr ( MachineFunction & MF )

static

Definition at line 3047 of file PPCISelLowering.cpp.

References llvm::MachineFunction::getInfo(), and llvm::PPCFunctionInfo::setUsesTOCBasePtr().

Referenced by llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), and setUsesTOCBasePtr().

◆ setUsesTOCBasePtr() [2/2]

void setUsesTOCBasePtr ( SelectionDAG & DAG )

static

Definition at line 3052 of file PPCISelLowering.cpp.

References llvm::SelectionDAG::getMachineFunction(), and setUsesTOCBasePtr().

◆ setXFormForUnalignedFI()

void setXFormForUnalignedFI	(	SDValue	N,
		unsigned	Flags,
		PPC::AddrMode &	Mode )

static

Definition at line 20691 of file PPCISelLowering.cpp.

References llvm::PPC::AM_DQForm, llvm::PPC::AM_DSForm, llvm::PPC::AM_XForm, llvm::isa(), Mode, llvm::PPC::MOF_RPlusSImm16Mult16, llvm::PPC::MOF_RPlusSImm16Mult4, and N.

Referenced by llvm::PPCTargetLowering::SelectOptimalAddrMode().

◆ signExtendOperandIfUnknown()

void signExtendOperandIfUnknown	(	MachineInstr &	MI,
		MachineBasicBlock *	BB,
		unsigned	OpIdx,
		bool	IsByte,
		const PPCInstrInfo *	TII )

static

Definition at line 13309 of file PPCISelLowering.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), F, isSignExtended(), MI, OpIdx, Reg, and TII.

Referenced by llvm::PPCTargetLowering::EmitAtomicBinary(), and llvm::PPCTargetLowering::EmitPartwordAtomicBinary().

◆ STATISTIC() [1/4]

STATISTIC	(	NumDynamicAllocaProbed	,
		"Number of dynamic stack allocation probed"	)

References MI, OpIdx, and TII.

◆ STATISTIC() [2/4]

STATISTIC	(	NumSiblingCalls	,
		"Number of sibling calls"	)

◆ STATISTIC() [3/4]

STATISTIC	(	NumTailCalls	,
		"Number of tail calls"	)

◆ STATISTIC() [4/4]

STATISTIC	(	ShufflesHandledWithVPERM	,
		"Number of shuffles lowered to a VPERM or XXPERM"	)

◆ StoreTailCallArgumentsToStackSlot()

void StoreTailCallArgumentsToStackSlot	(	SelectionDAG &	DAG,
		SDValue	Chain,
		const SmallVectorImpl< TailCallArgumentInfo > &	TailCallArgs,
		SmallVectorImpl< SDValue > &	MemOpChains,
		const SDLoc &	dl )

static

StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.

Definition at line 5122 of file PPCISelLowering.cpp.

References llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getStore(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SmallVectorTemplateCommon< T, typename >::size().

Referenced by PrepareTailCall().

◆ stripModuloOnShift()

SDValue stripModuloOnShift	(	const TargetLowering &	TLI,
		SDNode *	N,
		SelectionDAG &	DAG )

static

Definition at line 19714 of file PPCISelLowering.cpp.

References llvm::ISD::AND, llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValueType(), llvm::isConstOrConstSplat(), llvm::TargetLoweringBase::isOperationLegal(), llvm::EVT::isVector(), llvm_unreachable, N, SDValue(), llvm::ISD::SHL, llvm::ISD::SRA, and llvm::ISD::SRL.

◆ transformCallee()

SDValue transformCallee	(	const SDValue &	Callee,
		SelectionDAG &	DAG,
		const SDLoc &	dl,
		const PPCSubtarget &	Subtarget )

static

Definition at line 5433 of file PPCISelLowering.cpp.

References assert(), llvm::cast(), llvm::dyn_cast(), llvm::dyn_cast_or_null(), F, G, llvm::MachineFunction::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::TargetLoweringObjectFile::getFunctionEntryPointSymbol(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMCSymbol(), llvm::SectionKind::getMetadata(), llvm::TargetMachine::getObjFileLowering(), llvm::GlobalValue::getParent(), llvm::TargetLoweringBase::getPointerTy(), llvm::MCSectionXCOFF::getQualNameSymbol(), llvm::TargetMachine::getRelocationModel(), llvm::SelectionDAG::getTarget(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::PPCSubtarget::getTargetMachine(), llvm::PPCSubtarget::is32BitELFABI(), llvm::isa_and_nonnull(), llvm::PPCSubtarget::isAIXABI(), isBLACompatibleAddress(), llvm::PPCSubtarget::isELFv2ABI(), isFunctionGlobalAddress(), llvm::PPCII::MO_PLT, Mod, llvm::Reloc::PIC_, SDValue(), llvm::TargetMachine::shouldAssumeDSOLocal(), llvm::PPCSubtarget::usesFunctionDescriptors(), llvm::XCOFF::XMC_PR, and llvm::XCOFF::XTY_ER.

◆ truncateScalarIntegerArg()

SDValue truncateScalarIntegerArg	(	ISD::ArgFlagsTy	Flags,
		EVT	ValVT,
		SelectionDAG &	DAG,
		SDValue	ArgValue,
		MVT	LocVT,
		const SDLoc &	dl )

static

Definition at line 7072 of file PPCISelLowering.cpp.

References assert(), llvm::ISD::AssertSext, llvm::ISD::AssertZext, llvm::EVT::getFixedSizeInBits(), llvm::MVT::getFixedSizeInBits(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::EVT::isScalarInteger(), llvm::MVT::isScalarInteger(), and llvm::ISD::TRUNCATE.

◆ updateForAIXShLibTLSModelOpt()

void updateForAIXShLibTLSModelOpt	(	TLSModel::Model &	Model,
		SelectionDAG &	DAG,
		const TargetMachine &	TM )

static

updateForAIXShLibTLSModelOpt - Helper to initialize TLS model opt settings, and then apply the update.

Definition at line 3242 of file PPCISelLowering.cpp.

References llvm::dbgs(), llvm::dyn_cast(), llvm::format(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::MachineFunction::getName(), llvm::TargetMachine::getTLSModel(), I, llvm::TLSModel::InitialExec, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::PPCFunctionInfo::isAIXFuncTLSModelOptInitDone(), llvm::PPCFunctionInfo::isAIXFuncUseTLSIEForLD(), LLVM_DEBUG, llvm::TLSModel::LocalDynamic, PPCAIXTLSModelOptUseIEForLDLimit, llvm::PPCFunctionInfo::setAIXFuncTLSModelOptInitDone(), llvm::PPCFunctionInfo::setAIXFuncUseTLSIEForLD(), and llvm::SmallPtrSetImplBase::size().

◆ usePartialVectorLoads()

bool usePartialVectorLoads	(	SDNode *	N,
		const PPCSubtarget &	ST )

static

Returns true if we should use a direct load into vector instruction (such as lxsd or lfd), instead of a load into gpr + direct move sequence.

Definition at line 2884 of file PPCISelLowering.cpp.

References llvm::dyn_cast(), llvm::EVT::getSimpleVT(), llvm::Use::getUser(), llvm::SDValue::hasOneUse(), llvm::EVT::isSimple(), N, llvm::ISD::SCALAR_TO_VECTOR, and llvm::MVT::SimpleTy.

Referenced by llvm::PPCTargetLowering::getPreIndexedAddressParts().

◆ widenVec()

SDValue widenVec	(	SelectionDAG &	DAG,
		SDValue	Vec,
		const SDLoc &	dl )

static

Definition at line 8700 of file PPCISelLowering.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::ISD::CONCAT_VECTORS, llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), and llvm::EVT::isVector().

Variable Documentation

◆ AIXSmallTlsPolicySizeLimit

uint64_t AIXSmallTlsPolicySizeLimit = 32751

constexpr

Definition at line 174 of file PPCISelLowering.cpp.

◆ ANDIGlueBug

cl::opt<bool> ANDIGlueBug

extern

◆ DisableAutoPairedVecSt

cl::opt< bool > DisableAutoPairedVecSt("disable-auto-paired-vec-st", cl::desc("disable automatically generated 32byte paired vector stores"), cl::init(true), cl::Hidden)	(	"disable-auto-paired-vec-st"	,
		cl::desc("disable automatically generated 32byte paired vector stores")	,
		cl::init(true)	,
		cl::Hidden	)

Referenced by llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::lowerACCSpilling(), llvm::PPCRegisterInfo::lowerOctWordSpilling(), and llvm::PPCTargetLowering::PPCTargetLowering().

◆ DisableILPPref

cl::opt< bool > DisableILPPref("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)	(	"disable-ppc-ilp-pref"	,
		cl::desc("disable setting the node scheduling preference to ILP on PPC")	,
		cl::Hidden	)

static

Referenced by llvm::PPCTargetLowering::getSchedulingPreference().

◆ DisableInnermostLoopAlign32

cl::opt< bool > DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32", cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden)	(	"disable-ppc-innermost-loop-align32"	,
		cl::desc("don't always align innermost loop to 32 bytes on ppc")	,
		cl::Hidden	)

static

Referenced by llvm::PPCTargetLowering::getPrefLoopAlignment().

◆ DisableP10StoreForward

cl::opt< bool > DisableP10StoreForward("disable-p10-store-forward", cl::desc("disable P10 store forward-friendly conversion"), cl::Hidden, cl::init(false))	(	"disable-p10-store-forward"	,
		cl::desc("disable P10 store forward-friendly conversion")	,
		cl::Hidden	,
		cl::init(false)	)

static

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

◆ DisablePerfectShuffle

cl::opt< bool > DisablePerfectShuffle("ppc-disable-perfect-shuffle", cl::desc("disable vector permute decomposition"), cl::init(true), cl::Hidden)	(	"ppc-disable-perfect-shuffle"	,
		cl::desc("disable vector permute decomposition")	,
		cl::init(true)	,
		cl::Hidden	)

static

◆ DisablePPCPreinc

cl::opt< bool > DisablePPCPreinc("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)	(	"disable-ppc-preinc"	,
		cl::desc("disable preincrement load/store generation on PPC")	,
		cl::Hidden	)

static

Referenced by llvm::PPCTargetLowering::getPreIndexedAddressParts().

◆ DisablePPCUnaligned

cl::opt< bool > DisablePPCUnaligned("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)	(	"disable-ppc-unaligned"	,
		cl::desc("disable unaligned load/store generation on PPC")	,
		cl::Hidden	)

static

Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses().

◆ DisableSCO

cl::opt< bool > DisableSCO("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden)	(	"disable-ppc-sco"	,
		cl::desc("disable sibling call optimization on ppc")	,
		cl::Hidden	)

static

◆ FPR

const MCPhysReg FPR[]

static

Initial value:

= {PPC::F1,  PPC::F2,  PPC::F3, PPC::F4, PPC::F5,
                                PPC::F6,  PPC::F7,  PPC::F8, PPC::F9, PPC::F10,
                                PPC::F11, PPC::F12, PPC::F13}

FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.

Definition at line 4025 of file PPCISelLowering.cpp.

Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), CC_AIX(), and llvm::SystemZMachineFunctionInfo::setVarArgsFirstFPR().

◆ PPCAIXTLSModelOptUseIEForLDLimit

cl::opt< unsigned > PPCAIXTLSModelOptUseIEForLDLimit("ppc-aix-shared-lib-tls-model-opt-limit", cl::init(1), cl::Hidden, cl::desc("Set inclusive limit count of TLS local-dynamic access(es) in a " "function to use initial-exec"))	(	"ppc-aix-shared-lib-tls-model-opt-limit"	,
		cl::init(1)	,
		cl::Hidden	,
		cl::desc("Set inclusive limit count of TLS local-dynamic access(es) in a " "function to use initial-exec")	)

static

Referenced by updateForAIXShLibTLSModelOpt().

◆ PPCGatherAllAliasesMaxDepth

cl::opt< unsigned > PPCGatherAllAliasesMaxDepth("ppc-gather-alias-max-depth", cl::init(18), cl::Hidden, cl::desc("max depth when checking alias info in GatherAllAliases()"))	(	"ppc-gather-alias-max-depth"	,
		cl::init(18)	,
		cl::Hidden	,
		cl::desc("max depth when checking alias info in GatherAllAliases()")	)

static

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

◆ PPCMinimumBitTestCmps

cl::opt< unsigned > PPCMinimumBitTestCmps("ppc-min-bit-test-cmps", cl::init(3), cl::Hidden, cl::desc("Set minimum of largest number of comparisons to use bit test for " "switch on PPC."))	(	"ppc-min-bit-test-cmps"	,
		cl::init(3)	,
		cl::Hidden	,
		cl::desc("Set minimum of largest number of comparisons to use bit test for " "switch on PPC.")	)

static

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

◆ PPCMinimumJumpTableEntries

cl::opt< unsigned > PPCMinimumJumpTableEntries("ppc-min-jump-table-entries", cl::init(64), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table on PPC"))	(	"ppc-min-jump-table-entries"	,
		cl::init(64)	,
		cl::Hidden	,
		cl::desc("Set minimum number of entries to use a jump table on PPC")	)

static

Referenced by llvm::PPCTargetLowering::PPCTargetLowering().

◆ UseAbsoluteJumpTables

cl::opt< bool > UseAbsoluteJumpTables("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden)	(	"ppc-use-absolute-jumptables"	,
		cl::desc("use absolute jump tables on ppc")	,
		cl::Hidden	)

static

Referenced by llvm::PPCTargetLowering::isJumpTableRelative().

Macros

Typedefs

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

◆ GET_REGISTER_MATCHER

Typedef Documentation

◆ LXVKQPattern

Function Documentation

◆ addShuffleForVecExtend()

◆ AdjustLength()

◆ areCallingConvEligibleForTCO_64SVR4()

◆ buildCallOperands()

◆ BuildIntrinsicOp() [1/3]

◆ BuildIntrinsicOp() [2/3]

◆ BuildIntrinsicOp() [3/3]

◆ BuildVSLDOI()

◆ CalculateStackSlotAlignment()

◆ CalculateStackSlotSize()

◆ CalculateStackSlotUsed()

◆ CalculateTailCallArgDest()

◆ CalculateTailCallSPDiff()

◆ callIntrinsic()

◆ callsShareTOCBase()

◆ canConvertSETCCToXori()

◆ canConvertToVcmpequb()

◆ CC_AIX()

◆ combineADDToADDZE()

◆ combineADDToMAT_PCREL_ADDR()

◆ combineADDToSUB()

◆ combineBVOfConsecutiveLoads()

◆ combineBVOfVecSExt()

◆ combineBVZEXTLOAD()

◆ combineSELECT_CCBitFloor()

◆ combineXorSelectCC()

◆ combineZextSetccWithZero()

◆ computeFlagsForAddressComputation()

◆ ConvertCarryFlagToCarryValue()

◆ ConvertCarryValueToCarryFlag()

◆ convertFPToInt()

◆ convertIntToFP()

◆ ConvertSETCCToXori()

◆ convertTwoLoadsAndCmpToVCMPEQUB()

◆ createAtomicLoopBlocks()

◆ CreateCopyOfByValArgument()

◆ DAGCombineAddc()

◆ emitAtomicCmpSwapHardware()

◆ emitAtomicCmpSwapSoftware()

◆ emitSelect()

◆ EmitTailCallStoreFPAndRetAddr()

◆ EnsureStackAlignment()

◆ findConsecutiveLoad()

◆ fixupFuncForFI()

◆ fixupShuffleMaskForPermutedSToV()

◆ generateEquivalentSub()

◆ GeneratePerfectShuffle()

◆ generateSToVPermutedForVecShuffle()

◆ getBaseWithConstantOffset()

◆ getCallOpcode()

◆ getCanonicalConstSplat()

◆ getDataClassTest()

◆ getEstimateRefinementSteps()

◆ getIntrinsicForAtomicRMWBinOp128()

◆ getLabelAccessInfo()

◆ getMaxByValAlign()

◆ getNormalLoadInput()

◆ getOutputChainFromCallSeq()

◆ getPatternInfo()

◆ getPPCStrictOpcode()

◆ getRegClassForSVT()

◆ getSToVPermuted()

◆ getVectorCompareInfo()

◆ hasSameArgumentList()

◆ haveEfficientBuildVectorPattern()

◆ invertFMAOpcode()

◆ isAlternatingShuffMask()

◆ isBLACompatibleAddress()

◆ isConsecutiveLS()

◆ isConsecutiveLSLoc()