LLVM 24.0.0git
PPCSubtarget.cpp
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1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPC specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCSubtarget.h"
17#include "PPC.h"
18#include "PPCRegisterInfo.h"
19#include "PPCSelectionDAGInfo.h"
20#include "PPCTargetMachine.h"
25#include "llvm/IR/GlobalAlias.h"
26#include "llvm/IR/GlobalValue.h"
31
32using namespace llvm;
33
34#define DEBUG_TYPE "ppc-subtarget"
35
36#define GET_SUBTARGETINFO_TARGET_DESC
37#define GET_SUBTARGETINFO_CTOR
38#include "PPCGenSubtargetInfo.inc"
39
41 StringRef TuneCPU,
42 StringRef FS) {
43 initializeEnvironment();
44 initSubtargetFeatures(CPU, TuneCPU, FS);
45 return *this;
46}
47
49 StringRef FS, StringRef ABIName,
50 const PPCTargetMachine &TM)
51 : PPCGenSubtargetInfo(TT, CPU, TuneCPU, FS),
52 TargetABI(PPCTargetMachine::computeABI(TT, ABIName)), TM(TM),
54 InstrInfo(*this), TLInfo(TM, *this) {
55 TSInfo = std::make_unique<PPCSelectionDAGInfo>();
56
58 Legalizer.reset(new PPCLegalizerInfo(*this));
59 auto *RBI = new PPCRegisterBankInfo(*getRegisterInfo());
60 RegBankInfo.reset(RBI);
61
62 InstSelector.reset(createPPCInstructionSelector(TM, *this, *RBI));
63}
64
66
70
71void PPCSubtarget::initializeEnvironment() {
75}
76
77void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
78 StringRef FS) {
79 // Determine default and user specified characteristics
80 std::string CPUName = std::string(CPU);
81 if (CPUName.empty() || CPU == "generic") {
82 if (getTargetTriple().getSubArch() == Triple::PPCSubArch_spe)
83 CPUName = "e500";
84 else
85 CPUName = std::string(PPC::getNormalizedPPCTargetCPU(getTargetTriple()));
86 }
87
88 // Determine the CPU to schedule for.
89 if (TuneCPU.empty()) TuneCPU = CPUName;
90
91 // Initialize scheduling itinerary for the specified CPU.
92 InstrItins = getInstrItineraryForCPU(CPUName);
93
94 // Parse features string.
95 ParseSubtargetFeatures(CPUName, TuneCPU, FS);
96
97 // If the user requested use of 64-bit regs, but the cpu selected doesn't
98 // support it, ignore.
99 if (IsPPC64 && has64BitSupport())
100 Use64BitRegs = true;
101
102 if (getTargetTriple().isPPC32SecurePlt())
103 IsSecurePlt = true;
104
105 if (HasSPE && IsPPC64)
106 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
107 if (HasSPE && (HasAltivec || HasVSX || HasFPU))
109 "SPE and traditional floating point cannot both be enabled.\n", false);
110
111 // If not SPE, set standard FPU
112 if (!HasSPE)
113 HasFPU = true;
114
116
117 // Determine endianness.
118 IsLittleEndian = TM.isLittleEndian();
119
120 if (HasAIXSmallLocalExecTLS || HasAIXSmallLocalDynamicTLS) {
121 if (!getTargetTriple().isOSAIX() || !IsPPC64)
122 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute is "
123 "only supported on AIX in "
124 "64-bit mode.\n",
125 false);
126 // The aix-small-local-[exec|dynamic]-tls attribute should only be used with
127 // -data-sections, as having data sections turned off with this option
128 // is not ideal for performance. Moreover, the
129 // small-local-[exec|dynamic]-tls region is a limited resource, and should
130 // not be used for variables that may be replaced.
131 if (!TM.getDataSections())
132 report_fatal_error("The aix-small-local-[exec|dynamic]-tls attribute can "
133 "only be specified with "
134 "-data-sections.\n",
135 false);
136 }
137
138 if (HasAIXShLibTLSModelOpt && (!getTargetTriple().isOSAIX() || !IsPPC64))
139 report_fatal_error("The aix-shared-lib-tls-model-opt attribute "
140 "is only supported on AIX in 64-bit mode.\n",
141 false);
142
143 if (UsePointerGlueHelper && !getTargetTriple().isOSAIX())
144 report_fatal_error("use-ptrgl-helper feature is only supported on AIX\n",
145 false);
146}
147
148bool PPCSubtarget::enableMachineScheduler() const { return true; }
149
151 return getSchedModel().hasInstrSchedModel();
152}
153
154bool PPCSubtarget::useDFAforSMS() const { return false; }
155
156// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
157bool PPCSubtarget::enablePostRAScheduler() const { return true; }
158
159PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
160 return TargetSubtargetInfo::ANTIDEP_ALL;
161}
162
163void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
164 CriticalPathRCs.clear();
165 CriticalPathRCs.push_back(isPPC64() ?
166 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
167}
168
170 const SchedRegion &Region) const {
171 // The GenericScheduler that we use defaults to scheduling bottom up only.
172 // We want to schedule from both the top and the bottom and so we set
173 // OnlyBottomUp to false.
174 // We want to do bi-directional scheduling since it provides a more balanced
175 // schedule leading to better performance.
176 Policy.OnlyBottomUp = false;
177 // Spilling is generally expensive on all PPC cores, so always enable
178 // register-pressure tracking.
179 Policy.ShouldTrackPressure = true;
180}
181
183 return true;
184}
185
186bool PPCSubtarget::enableSubRegLiveness() const { return true; }
187
189 if (isAIXABI()) {
190 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
191 // On AIX the only symbols that aren't indirect are toc-data.
192 return !GVar->hasAttribute("toc-data");
193
194 return true;
195 }
196
197 // Large code model always uses the TOC even for local symbols.
198 if (TM.getCodeModel() == CodeModel::Large)
199 return true;
200
201 if (TM.shouldAssumeDSOLocal(GV))
202 return false;
203 return true;
204}
205
207 const GlobalValue *GV) const {
208 // If there isn't an attribute to override the module code model
209 // this will be the effective code model.
210 CodeModel::Model ModuleModel = TM.getCodeModel();
211
212 // Initially support per global code model for AIX only.
213 if (!isAIXABI())
214 return ModuleModel;
215
216 // Only GlobalVariables carry an attribute which can override the module code
217 // model.
218 assert(GV && "Unexpected NULL GlobalValue");
219 const GlobalVariable *GlobalVar =
220 [](const GlobalValue *GV) -> const GlobalVariable * {
222 if (Var)
223 return Var;
224
225 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
226 if (Alias)
228
229 return nullptr;
230 }(GV);
231
232 if (!GlobalVar)
233 return ModuleModel;
234
235 std::optional<CodeModel::Model> MaybeCodeModel = GlobalVar->getCodeModel();
236 if (MaybeCodeModel) {
237 CodeModel::Model CM = *MaybeCodeModel;
238 assert((CM == CodeModel::Small || CM == CodeModel::Large) &&
239 "invalid code model for AIX");
240 return CM;
241 }
242
243 return ModuleModel;
244}
245
247
249 return isPPC64() && hasPCRelativeMemops() && isELFv2ABI() &&
251}
252
253// GlobalISEL
255 return CallLoweringInfo.get();
256}
257
259 return RegBankInfo.get();
260}
261
263 return Legalizer.get();
264}
265
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for PowerPC.
This file declares the targeting of the RegisterBankInfo class for PowerPC.
LLVM_ABI const GlobalObject * getAliaseeObject() const
Definition Globals.cpp:730
This class provides the information for the PowerPC target legalizer for GlobalISel.
std::unique_ptr< InstructionSelector > InstSelector
bool enableMachinePipeliner() const override
Pipeliner customization.
bool useDFAforSMS() const override
Machine Pipeliner customization.
std::unique_ptr< LegalizerInfo > Legalizer
PPCTargetLowering TLInfo
PPCSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, const PPCTargetMachine &TM)
This constructor initializes the data members to match that of the specified triple.
PPCFrameLowering FrameLowering
bool isAIXABI() const
const CallLowering * getCallLowering() const override
const LegalizerInfo * getLegalizerInfo() const override
std::unique_ptr< RegisterBankInfo > RegBankInfo
~PPCSubtarget() override
POPCNTDKind HasPOPCNTD
InstrItineraryData InstrItins
Selected instruction itineraries (one entry per itinerary class.)
Align StackAlignment
stackAlignment - The minimum alignment known to hold of the stack frame on entry to the function and ...
PPCInstrInfo InstrInfo
void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override
bool isUsingPCRelativeCalls() const
bool enableSubRegLiveness() const override
const PPCTargetLowering * getTargetLowering() const override
InstructionSelector * getInstructionSelector() const override
unsigned CPUDirective
Which cpu directive was used.
AntiDepBreakMode getAntiDepBreakMode() const override
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool useAA() const override
PPCABI TargetABI
The selected ABI variant.
PPCSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS)
initializeSubtargetDependencies - Initializes using a CPU, a TuneCPU, and feature string so that we c...
CodeModel::Model getCodeModel(const TargetMachine &TM, const GlobalValue *GV) const
Calculates the effective code model for argument GV.
bool isELFv2ABI() const
Align getPlatformStackAlignment() const
const PPCTargetMachine & getTargetMachine() const
const PPCTargetMachine & TM
std::unique_ptr< const SelectionDAGTargetInfo > TSInfo
bool enableMachineScheduler() const override
Scheduling customization.
void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override
const RegisterBankInfo * getRegBankInfo() const override
const PPCRegisterInfo * getRegisterInfo() const override
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool enablePostRAScheduler() const override
This overrides the PostRAScheduler bit in the SchedModel for each CPU.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
Common code between 32-bit and 64-bit PowerPC targets.
Holds all the information related to register banks.
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
constexpr bool empty() const
Check if the string is empty.
Definition StringRef.h:141
Primary interface to the complete machine description for the target machine.
CodeModel::Model getCodeModel() const
Returns the code model.
Triple - Helper class for working with autoconf configuration names.
Definition Triple.h:48
@ PPCSubArch_spe
Definition Triple.h:173
LLVM_ABI StringRef getNormalizedPPCTargetCPU(const Triple &T, StringRef CPUName="")
This is an optimization pass for GlobalISel generic memory operations.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
Definition Error.cpp:163
InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI)
@ PPC_ABI_ELFv2
Definition PPC.h:104
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
A region of an MBB for scheduling.