LLVM 24.0.0git
TargetTransformInfo.cpp
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1//===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
10#include "llvm/ADT/Sequence.h"
12#include "llvm/Analysis/CFG.h"
16#include "llvm/IR/CFG.h"
17#include "llvm/IR/Dominators.h"
18#include "llvm/IR/Instruction.h"
21#include "llvm/IR/Module.h"
22#include "llvm/IR/Operator.h"
25#include <optional>
26#include <utility>
27
28using namespace llvm;
29using namespace PatternMatch;
30
31#define DEBUG_TYPE "tti"
32
34 "cache-line-size", cl::init(0), cl::Hidden,
35 cl::desc("Use this to override the target cache line size when "
36 "specified by the user."));
37
39 "min-page-size", cl::init(0), cl::Hidden,
40 cl::desc("Use this to override the target's minimum page size."));
41
43 "predictable-branch-threshold", cl::init(99), cl::Hidden,
45 "Use this to override the target's predictable branch threshold (%)."));
46
47namespace {
48/// No-op implementation of the TTI interface using the utility base
49/// classes.
50///
51/// This is used when no target specific information is available.
52struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
53 explicit NoTTIImpl(const DataLayout &DL)
54 : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
55};
56} // namespace
57
59 std::unique_ptr<const TargetTransformInfoImplBase> Impl)
60 : TTIImpl(std::move(Impl)) {}
61
63 // If the loop has irreducible control flow, it can not be converted to
64 // Hardware loop.
65 LoopBlocksRPO RPOT(L);
66 RPOT.perform(&LI);
68 return false;
69 return true;
70}
71
73 Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarizationCost,
74 bool TypeBasedOnly)
75 : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
76 ScalarizationCost(ScalarizationCost) {
77
78 if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
79 FMF = FPMO->getFastMathFlags();
80
81 if (!TypeBasedOnly)
82 Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
83 for (const Value *Arg : CI.args())
84 ParamTys.push_back(Arg->getType());
85}
86
89 FastMathFlags Flags,
90 const IntrinsicInst *I,
91 InstructionCost ScalarCost)
92 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
93 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
94}
95
98 : RetTy(Ty), IID(Id) {
99
100 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
101 ParamTys.reserve(Arguments.size());
102 for (const Value *Argument : Arguments)
103 ParamTys.push_back(Argument->getType());
104}
105
109 InstructionCost ScalarCost, VectorInstrContext VIC)
110 : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost),
111 VIC(VIC) {
112 ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
113 Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
114}
115
117 // Match default options:
118 // - hardware-loop-counter-bitwidth = 32
119 // - hardware-loop-decrement = 1
120 CountType = Type::getInt32Ty(L->getHeader()->getContext());
121 LoopDecrement = ConstantInt::get(CountType, 1);
122}
123
125 LoopInfo &LI, DominatorTree &DT,
126 bool ForceNestedLoop,
128 SmallVector<BasicBlock *, 4> ExitingBlocks;
129 L->getExitingBlocks(ExitingBlocks);
130
131 for (BasicBlock *BB : ExitingBlocks) {
132 // If we pass the updated counter back through a phi, we need to know
133 // which latch the updated value will be coming from.
134 if (!L->isLoopLatch(BB)) {
136 continue;
137 }
138
139 const SCEV *EC = SE.getExitCount(L, BB);
141 continue;
142 if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
143 if (ConstEC->getValue()->isZero())
144 continue;
145 } else if (!SE.isLoopInvariant(EC, L))
146 continue;
147
148 if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
149 continue;
150
151 // If this exiting block is contained in a nested loop, it is not eligible
152 // for insertion of the branch-and-decrement since the inner loop would
153 // end up messing up the value in the CTR.
154 if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
155 continue;
156
157 // We now have a loop-invariant count of loop iterations (which is not the
158 // constant zero) for which we know that this loop will not exit via this
159 // existing block.
160
161 // We need to make sure that this block will run on every loop iteration.
162 // For this to be true, we must dominate all blocks with backedges. Such
163 // blocks are in-loop predecessors to the header block.
164 bool NotAlways = false;
165 for (BasicBlock *Pred : predecessors(L->getHeader())) {
166 if (!L->contains(Pred))
167 continue;
168
169 if (!DT.dominates(BB, Pred)) {
170 NotAlways = true;
171 break;
172 }
173 }
174
175 if (NotAlways)
176 continue;
177
178 // Make sure this blocks ends with a conditional branch.
179 if (CondBrInst *BI = dyn_cast<CondBrInst>(BB->getTerminator()))
180 ExitBranch = BI;
181 else
182 continue;
183
184 // Note that this block may not be the loop latch block, even if the loop
185 // has a latch block.
186 ExitBlock = BB;
187 ExitCount = EC;
188 break;
189 }
190
191 if (!ExitBlock)
192 return false;
193 return true;
194}
195
197 : TTIImpl(std::make_unique<NoTTIImpl>(DL)) {}
198
200
203
205 TTIImpl = std::move(RHS.TTIImpl);
206 return *this;
207}
208
210 return TTIImpl->getInliningThresholdMultiplier();
211}
212
213unsigned
215 return TTIImpl->getInliningCostBenefitAnalysisSavingsMultiplier();
216}
217
218unsigned
220 const {
221 return TTIImpl->getInliningCostBenefitAnalysisProfitableMultiplier();
222}
223
225 return TTIImpl->getInliningLastCallToStaticBonus();
226}
227
228unsigned
230 return TTIImpl->adjustInliningThreshold(CB);
231}
232
234 const AllocaInst *AI) const {
235 return TTIImpl->getCallerAllocaCost(CB, AI);
236}
237
239 return TTIImpl->getInlinerVectorBonusPercent();
240}
241
243 Type *PointeeType, const Value *Ptr, ArrayRef<const Value *> Operands,
244 TTI::TargetCostKind CostKind, Type *AccessType) const {
245 return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind, AccessType);
246}
247
250 const TTI::PointersChainInfo &Info, Type *AccessTy,
251 TTI::TargetCostKind CostKind) const {
252 assert((Base || !Info.isSameBase()) &&
253 "If pointers have same base address it has to be provided.");
254 return TTIImpl->getPointersChainCost(Ptrs, Base, Info, AccessTy, CostKind);
255}
256
258 const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
259 BlockFrequencyInfo *BFI) const {
260 return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
261}
262
266 enum TargetCostKind CostKind) const {
267 InstructionCost Cost = TTIImpl->getInstructionCost(U, Operands, CostKind);
268 assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) &&
269 "TTI should not produce negative costs!");
270 return Cost;
271}
272
274 return PredictableBranchThreshold.getNumOccurrences() > 0
276 : TTIImpl->getPredictableBranchThreshold();
277}
278
280 return TTIImpl->getBranchMispredictPenalty();
281}
282
284 return TTIImpl->hasBranchDivergence(F);
285}
286
289 ValueUniformity VU = TTIImpl->getValueUniformity(V);
290 if (const auto *Call = dyn_cast<CallBase>(V)) {
292 Call->hasFnAttr(Attribute::NoDivergenceSource))
294 }
295 return VU;
296}
297
299 unsigned ToAS) const {
300 return TTIImpl->isValidAddrSpaceCast(FromAS, ToAS);
301}
302
304 unsigned ToAS) const {
305 return TTIImpl->addrspacesMayAlias(FromAS, ToAS);
306}
307
309 return TTIImpl->getFlatAddressSpace();
310}
311
313 unsigned AS2) const {
314 assert(AS1 != AS2 && "Expected distinct address spaces");
315 return TTIImpl->getAddressSpaceJoin(AS1, AS2);
316}
317
319 SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
320 return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
321}
322
324 unsigned ToAS) const {
325 return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
326}
327
328std::pair<KnownBits, KnownBits>
330 const Value &PtrOp) const {
331 return TTIImpl->computeKnownBitsAddrSpaceCast(ToAS, PtrOp);
332}
333
335 unsigned FromAS, unsigned ToAS, const KnownBits &FromPtrBits) const {
336 return TTIImpl->computeKnownBitsAddrSpaceCast(FromAS, ToAS, FromPtrBits);
337}
338
340 unsigned SrcAS, unsigned DstAS) const {
341 return TTIImpl->getAddrSpaceCastPreservedPtrMask(SrcAS, DstAS);
342}
343
345 unsigned AS) const {
346 return TTIImpl->canHaveNonUndefGlobalInitializerInAddressSpace(AS);
347}
348
350 return TTIImpl->getAssumedAddrSpace(V);
351}
352
353std::pair<const Value *, unsigned>
355 return TTIImpl->getPredicatedAddrSpace(V);
356}
357
359 IntrinsicInst *II, Value *OldV, Value *NewV) const {
360 return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
361}
362
364 return TTIImpl->isLoweredToCall(F);
365}
366
369 TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
370 return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
371}
372
374 return TTIImpl->getEpilogueVectorizationMinVF();
375}
376
378 TailFoldingInfo *TFI) const {
379 return TTIImpl->preferTailFoldingOverEpilogue(TFI);
380}
381
383 return TTIImpl->getPreferredTailFoldingStyle();
384}
385
386std::optional<Instruction *>
388 IntrinsicInst &II) const {
389 return TTIImpl->instCombineIntrinsic(IC, II);
390}
391
393 InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
394 bool &KnownBitsComputed) const {
395 return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
396 KnownBitsComputed);
397}
398
400 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
401 APInt &UndefElts2, APInt &UndefElts3,
402 std::function<void(Instruction *, unsigned, APInt, APInt &)>
403 SimplifyAndSetOp) const {
404 return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
405 IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
406 SimplifyAndSetOp);
407}
408
411 OptimizationRemarkEmitter *ORE) const {
412 return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
413}
414
416 PeelingPreferences &PP) const {
417 return TTIImpl->getPeelingPreferences(L, SE, PP);
418}
419
421 return TTIImpl->isLegalAddImmediate(Imm);
422}
423
425 return TTIImpl->isLegalAddScalableImmediate(Imm);
426}
427
429 return TTIImpl->isLegalICmpImmediate(Imm);
430}
431
433 const ICmpInst &Cond, const APInt &PostIncExitValue) const {
434 return TTIImpl->preferLoopExitWithEqualityComparison(Cond, PostIncExitValue);
435}
436
438 int64_t BaseOffset,
439 bool HasBaseReg, int64_t Scale,
440 unsigned AddrSpace,
441 Instruction *I,
442 int64_t ScalableOffset) const {
443 return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
444 Scale, AddrSpace, I, ScalableOffset);
445}
446
448 const LSRCost &C2) const {
449 return TTIImpl->isLSRCostLess(C1, C2);
450}
451
453 return TTIImpl->isNumRegsMajorCostOfLSR();
454}
455
457 return TTIImpl->shouldDropLSRSolutionIfLessProfitable();
458}
459
461 return TTIImpl->isProfitableLSRChainElement(I);
462}
463
465 return TTIImpl->canMacroFuseCmp();
466}
467
469 ScalarEvolution *SE, LoopInfo *LI,
471 TargetLibraryInfo *LibInfo) const {
472 return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
473}
474
477 ScalarEvolution *SE) const {
478 return TTIImpl->getPreferredAddressingMode(L, SE);
479}
480
482 unsigned AddressSpace,
483 TTI::MaskKind MaskKind) const {
484 return TTIImpl->isLegalMaskedStore(DataType, Alignment, AddressSpace,
485 MaskKind);
486}
487
489 unsigned AddressSpace,
490 TTI::MaskKind MaskKind) const {
491 return TTIImpl->isLegalMaskedLoad(DataType, Alignment, AddressSpace,
492 MaskKind);
493}
494
496 unsigned AddressSpace) const {
497 return TTIImpl->isLegalSpeculativeLoad(DataType, AddressSpace);
498}
499
501 Align Alignment) const {
502 return TTIImpl->isLegalNTStore(DataType, Alignment);
503}
504
505bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
506 return TTIImpl->isLegalNTLoad(DataType, Alignment);
507}
508
510 ElementCount NumElements) const {
511 return TTIImpl->isLegalBroadcastLoad(ElementTy, NumElements);
512}
513
515 Align Alignment) const {
516 return TTIImpl->isLegalMaskedGather(DataType, Alignment);
517}
518
520 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
521 const SmallBitVector &OpcodeMask, ArrayRef<const Value *> Scalars) const {
522 return TTIImpl->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask, Scalars);
523}
524
526 Align Alignment) const {
527 return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
528}
529
531 Align Alignment) const {
532 return TTIImpl->forceScalarizeMaskedGather(DataType, Alignment);
533}
534
536 Align Alignment) const {
537 return TTIImpl->forceScalarizeMaskedScatter(DataType, Alignment);
538}
539
541 Align Alignment) const {
542 return TTIImpl->isLegalMaskedCompressStore(DataType, Alignment);
543}
544
546 Align Alignment) const {
547 return TTIImpl->isLegalMaskedExpandLoad(DataType, Alignment);
548}
549
551 Align Alignment) const {
552 return TTIImpl->isLegalStridedLoadStore(DataType, Alignment);
553}
554
556 unsigned NumVectors, TTI::MaskSource Mask, VectorType *VectorTy,
557 bool IsStore, std::optional<Instruction::CastOps> CastHint) const {
558 return TTIImpl->hasMultiVectorLoadStore(NumVectors, Mask, VectorTy, IsStore,
559 CastHint);
560}
561
563 VectorType *VTy, unsigned Factor, Align Alignment,
564 unsigned AddrSpace) const {
565 return TTIImpl->isLegalInterleavedAccessType(VTy, Factor, Alignment,
566 AddrSpace);
567}
568
570 Type *DataType) const {
571 return TTIImpl->isLegalMaskedVectorHistogram(AddrType, DataType);
572}
573
575 return TTIImpl->enableOrderedReductions();
576}
577
578bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
579 return TTIImpl->hasDivRemOp(DataType, IsSigned);
580}
581
583 unsigned AddrSpace) const {
584 return TTIImpl->hasVolatileVariant(I, AddrSpace);
585}
586
588 return TTIImpl->prefersVectorizedAddressing();
589}
590
592 Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg,
593 int64_t Scale, unsigned AddrSpace) const {
594 InstructionCost Cost = TTIImpl->getScalingFactorCost(
595 Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace);
596 assert(Cost >= 0 && "TTI should not produce negative costs!");
597 return Cost;
598}
599
601 return TTIImpl->LSRWithInstrQueries();
602}
603
605 return TTIImpl->isTruncateFree(Ty1, Ty2);
606}
607
609 return TTIImpl->isProfitableToHoist(I);
610}
611
612bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
613
615 return TTIImpl->isTypeLegal(Ty);
616}
617
619 return TTIImpl->getRegUsageForType(Ty);
620}
621
623 return TTIImpl->shouldBuildLookupTables();
624}
625
627 Constant *C) const {
628 return TTIImpl->shouldBuildLookupTablesForConstant(C);
629}
630
632 return TTIImpl->getMinimumLookupTableEntryBitWidth();
633}
634
636 return TTIImpl->shouldBuildRelLookupTables();
637}
638
640 return TTIImpl->useColdCCForColdCall(F);
641}
642
644 return TTIImpl->useFastCCForInternalCall(F);
645}
646
648 Intrinsic::ID ID, unsigned ScalarOpdIdx) const {
649 return TTIImpl->isTargetIntrinsicWithScalarOpAtArg(ID, ScalarOpdIdx);
650}
651
653 Intrinsic::ID ID, int OpdIdx) const {
654 return TTIImpl->isTargetIntrinsicWithOverloadTypeAtArg(ID, OpdIdx);
655}
656
658 Intrinsic::ID ID, int RetIdx) const {
659 return TTIImpl->isTargetIntrinsicWithStructReturnOverloadAtField(ID, RetIdx);
660}
661
666 return Ctx1 == Ctx2 ? Ctx1 : TargetTransformInfo::VectorInstrContext::None;
667}
668
671 if (!I)
673
674 // For inserts, check if the value being inserted comes from a single-use
675 // load.
676 if (isa<InsertElementInst>(I) && isa<LoadInst>(I->getOperand(1)) &&
677 I->getOperand(1)->hasOneUse())
679
680 // For extracts, check if it has a single use that is a store.
681 if (isa<ExtractElementInst>(I) && I->hasOneUse() &&
682 isa<StoreInst>(*I->user_begin()))
684
686}
687
690 const APInt &DemandedElts) {
692 for (unsigned I : seq(VL.size())) {
693 if (!DemandedElts[I])
694 continue;
695 Value *V = VL[I];
696 if (isa<UndefValue>(V))
697 continue;
698 auto *Inst = dyn_cast<Instruction>(V);
699 if (!Inst)
702 if (VIC == VectorInstrContext::None) {
703 VIC = IVIC;
704 continue;
705 }
706 if (VIC != IVIC)
708 }
709 return VIC;
710}
711
714 ArrayRef<int> Mask, ArrayRef<Value *> Scalars,
716 const {
717 return TTIImpl->getBuildVectorContextHint(Mask, Scalars, GatherUseOps);
718}
719
721 VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract,
722 TTI::TargetCostKind CostKind, bool ForPoisonSrc, ArrayRef<Value *> VL,
723 TTI::VectorInstrContext VIC) const {
724 return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
725 CostKind, ForPoisonSrc, VL, VIC);
726}
727
730 TTI::VectorInstrContext VIC) const {
731 return TTIImpl->getOperandsScalarizationOverhead(Tys, CostKind, VIC);
732}
733
735 return TTIImpl->supportsEfficientVectorElementLoadStore();
736}
737
739 return TTIImpl->supportsTailCalls();
740}
741
743 return TTIImpl->supportsTailCallFor(CB);
744}
745
747 bool LoopHasReductions) const {
748 return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
749}
750
752TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
753 return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
754}
755
757 return TTIImpl->enableSelectOptimize();
758}
759
761 const Instruction *I) const {
762 return TTIImpl->shouldTreatInstructionLikeSelect(I);
763}
764
766 return TTIImpl->enableInterleavedAccessVectorization();
767}
768
770 return TTIImpl->enableMaskedInterleavedAccessVectorization();
771}
772
774 return TTIImpl->isFPVectorizationPotentiallyUnsafe();
775}
776
777bool
779 unsigned BitWidth,
780 unsigned AddressSpace,
781 Align Alignment,
782 unsigned *Fast) const {
783 return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
784 AddressSpace, Alignment, Fast);
785}
786
788TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
789 return TTIImpl->getPopcntSupport(IntTyWidthInBit);
790}
791
793 return TTIImpl->haveFastSqrt(Ty);
794}
795
797 const Instruction *I) const {
798 return TTIImpl->isExpensiveToSpeculativelyExecute(I);
799}
800
802 return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
803}
804
806 InstructionCost Cost = TTIImpl->getFPOpCost(Ty);
807 assert(Cost >= 0 && "TTI should not produce negative costs!");
808 return Cost;
809}
810
812 unsigned Idx,
813 const APInt &Imm,
814 Type *Ty) const {
815 InstructionCost Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
816 assert(Cost >= 0 && "TTI should not produce negative costs!");
817 return Cost;
818}
819
822 TTI::TargetCostKind CostKind) const {
823 InstructionCost Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
824 assert(Cost >= 0 && "TTI should not produce negative costs!");
825 return Cost;
826}
827
829 unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty,
830 TTI::TargetCostKind CostKind, Instruction *Inst) const {
832 TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
833 assert(Cost >= 0 && "TTI should not produce negative costs!");
834 return Cost;
835}
836
839 const APInt &Imm, Type *Ty,
840 TTI::TargetCostKind CostKind) const {
842 TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
843 assert(Cost >= 0 && "TTI should not produce negative costs!");
844 return Cost;
845}
846
848 const Instruction &Inst, const Function &Fn) const {
849 return TTIImpl->preferToKeepConstantsAttached(Inst, Fn);
850}
851
852unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
853 return TTIImpl->getNumberOfRegisters(ClassID);
854}
855
857 bool IsStore) const {
858 return TTIImpl->hasConditionalLoadStoreForType(Ty, IsStore);
859}
860
862 Type *Ty) const {
863 return TTIImpl->getRegisterClassForType(Vector, Ty);
864}
865
866const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
867 return TTIImpl->getRegisterClassName(ClassID);
868}
869
871 unsigned ClassID, TTI::TargetCostKind CostKind) const {
872 return TTIImpl->getRegisterClassSpillCost(ClassID, CostKind);
873}
874
876 unsigned ClassID, TTI::TargetCostKind CostKind) const {
877 return TTIImpl->getRegisterClassReloadCost(ClassID, CostKind);
878}
879
882 return TTIImpl->getRegisterBitWidth(K);
883}
884
886 return TTIImpl->getMinVectorRegisterBitWidth();
887}
888
889std::optional<unsigned> TargetTransformInfo::getVScaleForTuning() const {
890 return TTIImpl->getVScaleForTuning();
891}
892
895 return TTIImpl->shouldMaximizeVectorBandwidth(K);
896}
897
899 bool IsScalable) const {
900 return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
901}
902
903unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
904 unsigned Opcode) const {
905 return TTIImpl->getMaximumVF(ElemWidth, Opcode);
906}
907
908unsigned TargetTransformInfo::getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
909 Type *ScalarValTy,
910 Align Alignment,
911 unsigned AddrSpace) const {
912 return TTIImpl->getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy, Alignment,
913 AddrSpace);
914}
915
917 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
918 return TTIImpl->shouldConsiderAddressTypePromotion(
919 I, AllowPromotionWithoutCommonHeader);
920}
921
923 return CacheLineSize.getNumOccurrences() > 0 ? CacheLineSize
924 : TTIImpl->getCacheLineSize();
925}
926
927std::optional<unsigned>
929 return TTIImpl->getCacheSize(Level);
930}
931
932std::optional<unsigned>
934 return TTIImpl->getCacheAssociativity(Level);
935}
936
937std::optional<unsigned> TargetTransformInfo::getMinPageSize() const {
938 return MinPageSize.getNumOccurrences() > 0 ? MinPageSize
939 : TTIImpl->getMinPageSize();
940}
941
943 return TTIImpl->getPrefetchDistance();
944}
945
947 unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
948 unsigned NumPrefetches, bool HasCall) const {
949 return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
950 NumPrefetches, HasCall);
951}
952
954 return TTIImpl->getMaxPrefetchIterationsAhead();
955}
956
958 return TTIImpl->enableWritePrefetching();
959}
960
962 return TTIImpl->shouldPrefetchAddressSpace(AS);
963}
964
966 unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType,
968 PartialReductionExtendKind OpBExtend, std::optional<unsigned> BinOp,
969 TTI::TargetCostKind CostKind, std::optional<FastMathFlags> FMF) const {
970 return TTIImpl->getPartialReductionCost(Opcode, InputTypeA, InputTypeB,
971 AccumType, VF, OpAExtend, OpBExtend,
972 BinOp, CostKind, FMF);
973}
974
975unsigned
977 bool HasUnorderedReductions) const {
978 return TTIImpl->getMaxInterleaveFactor(VF, HasUnorderedReductions);
979}
980
985
986 // undef/poison don't materialize constants.
987 if (isa<UndefValue>(V))
988 return {OK_AnyValue, OP_None};
989
990 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
991 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
992 if (CI->getValue().isPowerOf2())
993 OpProps = OP_PowerOf2;
994 else if (CI->getValue().isNegatedPowerOf2())
995 OpProps = OP_NegatedPowerOf2;
996 }
997 return {OK_UniformConstantValue, OpProps};
998 }
999
1000 // A broadcast shuffle creates a uniform value.
1001 // TODO: Add support for non-zero index broadcasts.
1002 // TODO: Add support for different source vector width.
1003 if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
1004 if (ShuffleInst->isZeroEltSplat())
1005 OpInfo = OK_UniformValue;
1006
1007 const Value *Splat = getSplatValue(V);
1008
1009 // Check for a splat of a constant or for a non uniform vector of constants
1010 // and check if the constant(s) are all powers of two.
1011 if (Splat) {
1012 // Check for a splat of a uniform value. This is not loop aware, so return
1013 // true only for the obviously uniform cases (argument, globalvalue)
1015 OpInfo = OK_UniformValue;
1016 } else if (isa<Constant>(Splat)) {
1017 OpInfo = OK_UniformConstantValue;
1018 if (auto *CI = dyn_cast<ConstantInt>(Splat)) {
1019 if (CI->getValue().isPowerOf2())
1020 OpProps = OP_PowerOf2;
1021 else if (CI->getValue().isNegatedPowerOf2())
1022 OpProps = OP_NegatedPowerOf2;
1023 }
1024 }
1025 } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
1027 bool AllPow2 = true, AllNegPow2 = true;
1028 for (uint64_t I = 0, E = CDS->getNumElements(); I != E; ++I) {
1029 if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I))) {
1030 AllPow2 &= CI->getValue().isPowerOf2();
1031 AllNegPow2 &= CI->getValue().isNegatedPowerOf2();
1032 if (AllPow2 || AllNegPow2)
1033 continue;
1034 }
1035 AllPow2 = AllNegPow2 = false;
1036 break;
1037 }
1038 OpProps = AllPow2 ? OP_PowerOf2 : OpProps;
1039 OpProps = AllNegPow2 ? OP_NegatedPowerOf2 : OpProps;
1040 } else if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
1042 }
1043
1044 return {OpInfo, OpProps};
1045}
1046
1049 assert(!Ops.empty());
1050 const auto *Op0 = Ops.front();
1051
1052 const bool IsConstant = all_of(Ops, [](Value *V) {
1053 // TODO: We should allow undef elements here
1055 !isa<UndefValue>(V);
1056 });
1057 const bool IsUniform = all_of(Ops, [=](Value *V) {
1058 // TODO: We should allow undef elements here
1059 return V == Op0;
1060 });
1061 const bool IsPowerOfTwo = all_of(Ops, [](Value *V) {
1062 // TODO: We should allow undef elements here
1063 if (auto *CI = dyn_cast<ConstantInt>(V))
1064 return CI->getValue().isPowerOf2();
1065 return false;
1066 });
1067 const bool IsNegatedPowerOfTwo = all_of(Ops, [](Value *V) {
1068 // TODO: We should allow undef elements here
1069 if (auto *CI = dyn_cast<ConstantInt>(V))
1070 return CI->getValue().isNegatedPowerOf2();
1071 return false;
1072 });
1073
1075 if (IsConstant && IsUniform)
1077 else if (IsConstant)
1079 else if (IsUniform)
1081
1083 VP = IsPowerOfTwo ? TTI::OP_PowerOf2 : VP;
1084 VP = IsNegatedPowerOfTwo ? TTI::OP_NegatedPowerOf2 : VP;
1085
1086 return {VK, VP};
1087}
1088
1092 if (X == Y)
1093 return OpInfoX;
1094 return OpInfoX.mergeWith(getOperandInfo(Y));
1095}
1096
1098 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
1099 OperandValueInfo Op1Info, OperandValueInfo Op2Info,
1100 ArrayRef<const Value *> Args, const Instruction *CtxI,
1101 const TargetLibraryInfo *TLibInfo) const {
1102
1103 // Use call cost for frem instructions that have platform specific vector math
1104 // functions, as those will be replaced with calls later by SelectionDAG or
1105 // ReplaceWithVecLib pass.
1106 if (TLibInfo && Opcode == Instruction::FRem) {
1107 VectorType *VecTy = dyn_cast<VectorType>(Ty);
1108 LibFunc Func = TLibInfo->getLibFunc(Instruction::FRem, Ty->getScalarType());
1109 if (VecTy && Func != NotLibFunc &&
1110 TLibInfo->isFunctionVectorizable(TLibInfo->getName(Func),
1111 VecTy->getElementCount()))
1112 return getCallInstrCost(nullptr, VecTy, {VecTy, VecTy}, CostKind);
1113 }
1114
1115 InstructionCost Cost = TTIImpl->getArithmeticInstrCost(
1116 Opcode, Ty, CostKind, Op1Info, Op2Info, Args, CtxI);
1117 assert(Cost >= 0 && "TTI should not produce negative costs!");
1118 return Cost;
1119}
1120
1122 VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
1123 const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind,
1124 ArrayRef<const Value *> Scalars) const {
1125 InstructionCost Cost = TTIImpl->getAltInstrCost(
1126 VecTy, Opcode0, Opcode1, OpcodeMask, CostKind, Scalars);
1127 assert(Cost >= 0 && "TTI should not produce negative costs!");
1128 return Cost;
1129}
1130
1132 ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy,
1133 TTI::TargetCostKind CostKind, ArrayRef<int> Mask, int Index,
1134 VectorType *SubTp, ArrayRef<const Value *> Args, const Instruction *CtxI,
1135 TTI::VectorInstrContext VIC) const {
1136 assert((Mask.empty() || DstTy->isScalableTy() ||
1137 Mask.size() == DstTy->getElementCount().getKnownMinValue()) &&
1138 "Expected the Mask to match the return size if given");
1139 assert(SrcTy->getScalarType() == DstTy->getScalarType() &&
1140 "Expected the same scalar types");
1141 InstructionCost Cost = TTIImpl->getShuffleCost(
1142 Kind, DstTy, SrcTy, CostKind, Mask, Index, SubTp, Args, CtxI, VIC);
1143 assert(Cost >= 0 && "TTI should not produce negative costs!");
1144 return Cost;
1145}
1146
1149 if (auto *Cast = dyn_cast<CastInst>(I))
1150 return getPartialReductionExtendKind(Cast->getOpcode());
1151 return PR_None;
1152}
1153
1157 switch (Kind) {
1159 return Instruction::CastOps::ZExt;
1161 return Instruction::CastOps::SExt;
1163 return Instruction::CastOps::FPExt;
1164 default:
1165 break;
1166 }
1167 llvm_unreachable("Unhandled partial reduction extend kind");
1168}
1169
1172 Instruction::CastOps CastOpc) {
1173 switch (CastOpc) {
1174 case Instruction::CastOps::ZExt:
1175 return PR_ZeroExtend;
1176 case Instruction::CastOps::SExt:
1177 return PR_SignExtend;
1178 case Instruction::CastOps::FPExt:
1179 return PR_FPExtend;
1180 default:
1181 return PR_None;
1182 }
1183 llvm_unreachable("Unhandled cast opcode");
1184}
1185
1188 if (!I)
1189 return CastContextHint::None;
1190
1191 auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
1192 unsigned GatScatOp) {
1194 if (!I)
1195 return CastContextHint::None;
1196
1197 if (I->getOpcode() == LdStOp)
1199
1200 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1201 if (II->getIntrinsicID() == MaskedOp)
1203 if (II->getIntrinsicID() == GatScatOp)
1205 }
1206
1208 };
1209
1210 switch (I->getOpcode()) {
1211 case Instruction::ZExt:
1212 case Instruction::SExt:
1213 case Instruction::FPExt:
1214 return getLoadStoreKind(I->getOperand(0), Instruction::Load,
1215 Intrinsic::masked_load, Intrinsic::masked_gather);
1216 case Instruction::Trunc:
1217 case Instruction::FPTrunc:
1218 if (I->hasOneUse())
1219 return getLoadStoreKind(*I->user_begin(), Instruction::Store,
1220 Intrinsic::masked_store,
1221 Intrinsic::masked_scatter);
1222 break;
1223 default:
1224 return CastContextHint::None;
1225 }
1226
1228}
1229
1231 unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH,
1232 TTI::TargetCostKind CostKind, const Instruction *I) const {
1233 assert((I == nullptr || I->getOpcode() == Opcode) &&
1234 "Opcode should reflect passed instruction.");
1236 TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
1237 assert(Cost >= 0 && "TTI should not produce negative costs!");
1238 return Cost;
1239}
1240
1242 unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index,
1243 TTI::TargetCostKind CostKind) const {
1245 TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index, CostKind);
1246 assert(Cost >= 0 && "TTI should not produce negative costs!");
1247 return Cost;
1248}
1249
1251 unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I) const {
1252 assert((I == nullptr || I->getOpcode() == Opcode) &&
1253 "Opcode should reflect passed instruction.");
1254 InstructionCost Cost = TTIImpl->getCFInstrCost(Opcode, CostKind, I);
1255 assert(Cost >= 0 && "TTI should not produce negative costs!");
1256 return Cost;
1257}
1258
1260 unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred,
1261 TTI::TargetCostKind CostKind, OperandValueInfo Op1Info,
1262 OperandValueInfo Op2Info, const Instruction *I) const {
1263 assert((I == nullptr || I->getOpcode() == Opcode) &&
1264 "Opcode should reflect passed instruction.");
1265 InstructionCost Cost = TTIImpl->getCmpSelInstrCost(
1266 Opcode, ValTy, CondTy, VecPred, CostKind, Op1Info, Op2Info, I);
1267 assert(Cost >= 0 && "TTI should not produce negative costs!");
1268 return Cost;
1269}
1270
1272 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1273 const Value *Op0, const Value *Op1, TTI::VectorInstrContext VIC) const {
1274 assert((Opcode == Instruction::InsertElement ||
1275 Opcode == Instruction::ExtractElement) &&
1276 "Expecting Opcode to be insertelement/extractelement.");
1278 TTIImpl->getVectorInstrCost(Opcode, Val, CostKind, Index, Op0, Op1, VIC);
1279 assert(Cost >= 0 && "TTI should not produce negative costs!");
1280 return Cost;
1281}
1282
1284 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index,
1285 Value *Scalar, ArrayRef<std::tuple<Value *, User *, int>> ScalarUserAndIdx,
1286 TTI::VectorInstrContext VIC) const {
1287 assert((Opcode == Instruction::InsertElement ||
1288 Opcode == Instruction::ExtractElement) &&
1289 "Expecting Opcode to be insertelement/extractelement.");
1290 InstructionCost Cost = TTIImpl->getVectorInstrCost(
1291 Opcode, Val, CostKind, Index, Scalar, ScalarUserAndIdx, VIC);
1292 assert(Cost >= 0 && "TTI should not produce negative costs!");
1293 return Cost;
1294}
1295
1297 const Instruction &I, Type *Val, TTI::TargetCostKind CostKind,
1298 unsigned Index, TTI::VectorInstrContext VIC) const {
1299 // FIXME: Assert that Opcode is either InsertElement or ExtractElement.
1300 // This is mentioned in the interface description and respected by all
1301 // callers, but never asserted upon.
1303 TTIImpl->getVectorInstrCost(I, Val, CostKind, Index, VIC);
1304 assert(Cost >= 0 && "TTI should not produce negative costs!");
1305 return Cost;
1306}
1307
1309 unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind,
1310 unsigned Index) const {
1312 TTIImpl->getIndexedVectorInstrCostFromEnd(Opcode, Val, CostKind, Index);
1313 assert(Cost >= 0 && "TTI should not produce negative costs!");
1314 return Cost;
1315}
1316
1318 unsigned Opcode, TTI::TargetCostKind CostKind) const {
1319 assert((Opcode == Instruction::InsertValue ||
1320 Opcode == Instruction::ExtractValue) &&
1321 "Expecting Opcode to be insertvalue/extractvalue.");
1322 InstructionCost Cost = TTIImpl->getInsertExtractValueCost(Opcode, CostKind);
1323 assert(Cost >= 0 && "TTI should not produce negative costs!");
1324 return Cost;
1325}
1326
1328 Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts,
1329 TTI::TargetCostKind CostKind) const {
1330 InstructionCost Cost = TTIImpl->getReplicationShuffleCost(
1331 EltTy, ReplicationFactor, VF, DemandedDstElts, CostKind);
1332 assert(Cost >= 0 && "TTI should not produce negative costs!");
1333 return Cost;
1334}
1335
1337 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1339 const Instruction *I) const {
1340 assert((I == nullptr || I->getOpcode() == Opcode) &&
1341 "Opcode should reflect passed instruction.");
1342 InstructionCost Cost = TTIImpl->getMemoryOpCost(
1343 Opcode, Src, Alignment, AddressSpace, CostKind, OpInfo, I);
1344 assert(Cost >= 0 && "TTI should not produce negative costs!");
1345 return Cost;
1346}
1347
1349 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1350 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1351 bool UseMaskForCond, bool UseMaskForGaps) const {
1352 InstructionCost Cost = TTIImpl->getInterleavedMemoryOpCost(
1353 Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
1354 UseMaskForCond, UseMaskForGaps);
1355 assert(Cost >= 0 && "TTI should not produce negative costs!");
1356 return Cost;
1357}
1358
1361 TTI::TargetCostKind CostKind) const {
1362 InstructionCost Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
1363 assert(Cost >= 0 && "TTI should not produce negative costs!");
1364 return Cost;
1365}
1366
1368 const MemIntrinsicCostAttributes &MICA,
1369 TTI::TargetCostKind CostKind) const {
1370 InstructionCost Cost = TTIImpl->getMemIntrinsicInstrCost(MICA, CostKind);
1371 assert(Cost >= 0 && "TTI should not produce negative costs!");
1372 return Cost;
1373}
1374
1377 ArrayRef<Type *> Tys,
1378 TTI::TargetCostKind CostKind) const {
1379 InstructionCost Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
1380 assert(Cost >= 0 && "TTI should not produce negative costs!");
1381 return Cost;
1382}
1383
1385 return TTIImpl->getNumberOfParts(Tp);
1386}
1387
1389 Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr,
1390 TTI::TargetCostKind CostKind) const {
1392 TTIImpl->getAddressComputationCost(PtrTy, SE, Ptr, CostKind);
1393 assert(Cost >= 0 && "TTI should not produce negative costs!");
1394 return Cost;
1395}
1396
1398 InstructionCost Cost = TTIImpl->getMemcpyCost(I);
1399 assert(Cost >= 0 && "TTI should not produce negative costs!");
1400 return Cost;
1401}
1402
1404 return TTIImpl->getMaxMemIntrinsicInlineSizeThreshold();
1405}
1406
1408 return TTIImpl->getMaxBoundedMemSetInlineSize();
1409}
1410
1412 unsigned Opcode, VectorType *Ty, std::optional<FastMathFlags> FMF,
1413 TTI::TargetCostKind CostKind) const {
1415 TTIImpl->getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
1416 assert(Cost >= 0 && "TTI should not produce negative costs!");
1417 return Cost;
1418}
1419
1422 TTI::TargetCostKind CostKind) const {
1424 TTIImpl->getMinMaxReductionCost(IID, Ty, FMF, CostKind);
1425 assert(Cost >= 0 && "TTI should not produce negative costs!");
1426 return Cost;
1427}
1428
1430 unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1431 std::optional<FastMathFlags> FMF, TTI::TargetCostKind CostKind) const {
1432 return TTIImpl->getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
1433 CostKind);
1434}
1435
1437 bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty,
1438 TTI::TargetCostKind CostKind) const {
1439 return TTIImpl->getMulAccReductionCost(IsUnsigned, RedOpcode, ResTy, Ty,
1440 CostKind);
1441}
1442
1445 return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
1446}
1447
1449 MemIntrinsicInfo &Info) const {
1450 return TTIImpl->getTgtMemIntrinsic(Inst, Info);
1451}
1452
1454 return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
1455}
1456
1458 IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate) const {
1459 return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType,
1460 CanCreate);
1461}
1462
1464 LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
1465 unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
1466 std::optional<uint32_t> AtomicElementSize) const {
1467 return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
1468 DestAddrSpace, SrcAlign, DestAlign,
1469 AtomicElementSize);
1470}
1471
1473 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
1474 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1475 Align SrcAlign, Align DestAlign,
1476 std::optional<uint32_t> AtomicCpySize) const {
1477 TTIImpl->getMemcpyLoopResidualLoweringType(
1478 OpsOut, Context, RemainingBytes, SrcAddrSpace, DestAddrSpace, SrcAlign,
1479 DestAlign, AtomicCpySize);
1480}
1481
1483 const Function *Callee) const {
1484 return TTIImpl->areInlineCompatible(Caller, Callee);
1485}
1486
1487unsigned
1489 const CallBase &Call,
1490 unsigned DefaultCallPenalty) const {
1491 return TTIImpl->getInlineCallPenalty(F, Call, DefaultCallPenalty);
1492}
1493
1495 const Function *Caller, const Attribute &Attr) const {
1496 return TTIImpl->shouldCopyAttributeWhenOutliningFrom(Caller, Attr);
1497}
1499 const Function *Callee,
1500 ArrayRef<Type *> Types) const {
1501 return TTIImpl->areTypesABICompatible(Caller, Callee, Types);
1502}
1503
1505 Type *Ty) const {
1506 return TTIImpl->isIndexedLoadLegal(Mode, Ty);
1507}
1508
1510 Type *Ty) const {
1511 return TTIImpl->isIndexedStoreLegal(Mode, Ty);
1512}
1513
1515 return TTIImpl->getLoadStoreVecRegBitWidth(AS);
1516}
1517
1519 return TTIImpl->isLegalToVectorizeLoad(LI);
1520}
1521
1523 return TTIImpl->isLegalToVectorizeStore(SI);
1524}
1525
1527 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1528 return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
1529 AddrSpace);
1530}
1531
1533 unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
1534 return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
1535 AddrSpace);
1536}
1537
1539 const RecurrenceDescriptor &RdxDesc, ElementCount VF) const {
1540 return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1541}
1542
1544 return TTIImpl->isElementTypeLegalForScalableVector(Ty);
1545}
1546
1548 unsigned LoadSize,
1549 unsigned ChainSizeInBytes,
1550 VectorType *VecTy) const {
1551 return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1552}
1553
1555 unsigned StoreSize,
1556 unsigned ChainSizeInBytes,
1557 VectorType *VecTy) const {
1558 return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1559}
1560
1562 return TTIImpl->preferFixedOverScalableIfEqualCost();
1563}
1564
1566 Type *Ty) const {
1567 return TTIImpl->preferInLoopReduction(Kind, Ty);
1568}
1569
1571 return TTIImpl->preferAlternateOpcodeVectorization();
1572}
1573
1575 return TTIImpl->preferSLPInstCountCheck();
1576}
1577
1579 return TTIImpl->preferPredicatedReductionSelect();
1580}
1581
1583 ElementCount Iters) const {
1584 return TTIImpl->preferEpilogueVectorization(Iters);
1585}
1586
1588 return TTIImpl->shouldConsiderVectorizationRegPressure();
1589}
1590
1593 return TTIImpl->getVPLegalizationStrategy(VPI);
1594}
1595
1597 return TTIImpl->hasArmWideBranch(Thumb);
1598}
1599
1601 return TTIImpl->getFeatureMask(F);
1602}
1603
1605 return TTIImpl->getPriorityMask(F);
1606}
1607
1609 return TTIImpl->isMultiversionedFunction(F);
1610}
1611
1613 return TTIImpl->getMaxNumArgs();
1614}
1615
1617 return TTIImpl->shouldExpandReduction(II);
1618}
1619
1622 const IntrinsicInst *II) const {
1623 return TTIImpl->getPreferredExpandedReductionShuffle(II);
1624}
1625
1627 return TTIImpl->getGISelRematGlobalCost();
1628}
1629
1631 return TTIImpl->getMinTripCountTailFoldingThreshold();
1632}
1633
1635 return TTIImpl->supportsScalableVectors();
1636}
1637
1639 return TTIImpl->enableScalableVectorization();
1640}
1641
1643 return TTIImpl->hasActiveVectorLength();
1644}
1645
1648 const LoopInfo *LI) const {
1649 return TTIImpl->isProfitableToSinkOperands(I, OpsToSink, LI);
1650}
1651
1653 return TTIImpl->isVectorShiftByScalarCheap(Ty);
1654}
1655
1657 const Function &F,
1658 SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const {
1659 return TTIImpl->collectKernelLaunchBounds(F, LB);
1660}
1661
1663 return TTIImpl->allowVectorElementIndexingUsingGEP();
1664}
1665
1667 const SmallBitVector &UniformArgs) const {
1668 return TTIImpl->isUniform(I, UniformArgs);
1669}
1670
1672
1673TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1674
1676 std::function<Result(const Function &)> TTICallback)
1677 : TTICallback(std::move(TTICallback)) {}
1678
1681 assert(!F.isIntrinsic() && "Should not request TTI for intrinsics");
1682 return TTICallback(F);
1683}
1684
1685AnalysisKey TargetIRAnalysis::Key;
1686
1687TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1688 return Result(F.getDataLayout());
1689}
1690
1691// Register the basic pass.
1693 "Target Transform Information", false, true)
1695
1696void TargetTransformInfoWrapperPass::anchor() {}
1697
1700
1704
1706 FunctionAnalysisManager DummyFAM;
1707 TTI = TIRA.run(F, DummyFAM);
1708 return *TTI;
1709}
1710
for(const MachineOperand &MO :llvm::drop_begin(OldMI.operands(), Desc.getNumOperands()))
bool IsScalable
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
uint64_t Imm
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
#define X(NUM, ENUM, NAME)
Definition ELF.h:665
static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
Module.h This file contains the declarations for the Module class.
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
#define F(x, y, z)
Definition MD5.cpp:54
#define I(x, y, z)
Definition MD5.cpp:57
uint64_t IntrinsicInst * II
if(PassOpts->AAPipeline)
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
SmallVector< MachineOperand, 4 > Cond
int64_t C1
SI Fold Operands
Provides some synthesis utilities to produce sequences of values.
This file defines the SmallVector class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
static SymbolRef::Type getType(const Symbol *Sym)
Definition TapiFile.cpp:39
This file provides helpers for the implementation of a TargetTransformInfo-conforming class.
static cl::opt< unsigned > PredictableBranchThreshold("predictable-branch-threshold", cl::init(99), cl::Hidden, cl::desc("Use this to override the target's predictable branch threshold (%)."))
static cl::opt< unsigned > MinPageSize("min-page-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target's minimum page size."))
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition APInt.h:78
an instruction to allocate memory on the stack
This class represents an incoming formal argument to a Function.
Definition Argument.h:32
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
iterator end() const
Definition ArrayRef.h:130
size_t size() const
Get the array size.
Definition ArrayRef.h:141
iterator begin() const
Definition ArrayRef.h:129
A cache of @llvm.assume calls within a function.
Functions, function parameters, and return types can have attributes to indicate how they should be t...
Definition Attributes.h:106
LLVM Basic Block Representation.
Definition BasicBlock.h:62
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
iterator_range< User::op_iterator > args()
Iteration adapter for range-for loops.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition InstrTypes.h:740
Conditional Branch instruction.
This is an important base class in LLVM.
Definition Constant.h:44
A parsed version of the target data layout string in and methods for querying it.
Definition DataLayout.h:64
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition Dominators.h:122
LLVM_ABI bool dominates(const BasicBlock *BB, const Use &U) const
Return true if the (end of the) basic block BB dominates the use U.
Convenience struct for specifying and reasoning about fast-math flags.
Definition FMF.h:23
This instruction compares its operands according to the predicate given to the constructor.
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition Pass.h:283
ImmutablePass(char &pid)
Definition Pass.h:285
The core instruction combiner logic.
LLVM_ABI IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
Definition LLVMContext.h:76
An instruction for reading from memory.
Wrapper class to LoopBlocksDFS that provides a standard begin()/end() interface for the DFS reverse p...
void perform(const LoopInfo *LI)
Traverse the loop blocks and store the DFS result.
LoopT * getLoopFor(const BlockT *BB) const
Return the inner most loop that BB lives in.
Represents a single loop in the control flow graph.
Definition LoopInfo.h:40
Information for memory intrinsic cost model.
The optimization diagnostic interface.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
This class represents a constant integer value.
This class represents an analyzed expression in the program.
The main scalar evolution driver.
LLVM_ABI uint64_t getTypeSizeInBits(Type *Ty) const
Return the size in bits of the specified type, for which isSCEVable must return true.
LLVM_ABI bool isLoopInvariant(const SCEV *S, const Loop *L)
Return true if the value of the given SCEV is unchanging in the specified loop.
LLVM_ABI const SCEV * getExitCount(const Loop *L, const BasicBlock *ExitingBlock, ExitCountKind Kind=Exact)
Return the number of times the backedge executes before the given exit would be taken; if not exactly...
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:31
An instruction for storing to memory.
Multiway switch.
Analysis pass providing the TargetTransformInfo.
LLVM_ABI Result run(const Function &F, FunctionAnalysisManager &)
LLVM_ABI TargetIRAnalysis()
Default construct a target IR analysis.
Provides information about what library functions are available for the current target.
StringRef getName(LibFunc F) const
bool isFunctionVectorizable(StringRef F, const ElementCount &VF) const
LibFunc getLibFunc(StringRef funcName) const
Searches for a particular function name.
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
Wrapper pass for TargetTransformInfo.
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
TargetTransformInfo & getTTI(const Function &F)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
LLVM_ABI bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
LLVM_ABI Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType, bool CanCreate=true) const
LLVM_ABI bool isLegalToVectorizeLoad(LoadInst *LI) const
LLVM_ABI std::optional< unsigned > getVScaleForTuning() const
LLVM_ABI uint64_t getMaxBoundedMemSetInlineSize() const
Returns the maximum length in bytes for which a memset with a non-constant length,...
static LLVM_ABI CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
LLVM_ABI unsigned getMaxNumArgs() const
LLVM_ABI bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
Return false if a AS0 address cannot possibly alias a AS1 address.
LLVM_ABI bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
LLVM_ABI bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
LLVM_ABI VectorInstrContext getBuildVectorContextHint(ArrayRef< int > Mask, ArrayRef< Value * > Scalars, function_ref< bool(SmallVectorImpl< BuildVectorUseOp > &)> GatherUseOps) const
Calculates a VectorInstrContext for buildvector-like gather sequences.
LLVM_ABI bool isLegalToVectorizeStore(StoreInst *SI) const
LLVM_ABI bool areTypesABICompatible(const Function *Caller, const Function *Callee, ArrayRef< Type * > Types) const
LLVM_ABI bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
LLVM_ABI bool isLegalSpeculativeLoad(Type *DataType, unsigned AddressSpace) const
Return true if the target supports speculatively loading DataType from address space AddressSpace,...
LLVM_ABI bool isMultiversionedFunction(const Function &F) const
Returns true if this is an instance of a function with multiple versions.
LLVM_ABI unsigned getMaxInterleaveFactor(ElementCount VF, bool HasUnorderedReductions) const
LLVM_ABI bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
LLVM_ABI bool isLegalMaskedStore(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked store.
LLVM_ABI unsigned getMinimumLookupTableEntryBitWidth() const
Return the minimum bit width to use for integer switch lookup table elements on this target.
LLVM_ABI bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
LLVM_ABI unsigned getAssumedAddrSpace(const Value *V) const
LLVM_ABI bool preferAlternateOpcodeVectorization() const
LLVM_ABI bool shouldDropLSRSolutionIfLessProfitable() const
Return true if LSR should drop a found solution if it's calculated to be less profitable than the bas...
LLVM_ABI bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
LLVM_ABI unsigned getPrefetchDistance() const
LLVM_ABI Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicElementSize=std::nullopt) const
LLVM_ABI bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked expand load.
LLVM_ABI bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
LLVM_ABI InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI bool hasBranchDivergence(const Function *F=nullptr) const
Return true if branch divergence exists.
LLVM_ABI bool preferEpilogueVectorization(ElementCount Iters) const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop if t...
LLVM_ABI MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
LLVM_ABI void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
LLVM_ABI bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
LLVM_ABI InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind, Type *AccessType=nullptr) const
Estimate the cost of a GEP operation when lowered.
LLVM_ABI TailFoldingStyle getPreferredTailFoldingStyle() const
Query the target what the preferred style of tail folding is.
LLVM_ABI bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
LLVM_ABI std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
LLVM_ABI bool isProfitableLSRChainElement(Instruction *I) const
LLVM_ABI TypeSize getRegisterBitWidth(RegisterKind K) const
MaskKind
Some targets only support masked load/store with a constant mask.
LLVM_ABI unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
Returns a penalty for invoking call Call in F.
LLVM_ABI InstructionCost getOperandsScalarizationOverhead(ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing operands with the given types.
LLVM_ABI bool hasActiveVectorLength() const
LLVM_ABI bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
LLVM_ABI InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
LLVM_ABI ValueUniformity getValueUniformity(const Value *V) const
Get target-specific uniformity information for a value.
static LLVM_ABI OperandValueInfo commonOperandInfo(const Value *X, const Value *Y)
Collect common data between two OperandValueInfo inputs.
LLVM_ABI InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind) const
LLVM_ABI bool allowVectorElementIndexingUsingGEP() const
Returns true if GEP should not be used to index into vectors for this target.
LLVM_ABI bool preferTailFoldingOverEpilogue(TailFoldingInfo *TFI) const
Query the target whether it would be preferred to create a tail-folded vector loop,...
LLVM_ABI std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
LLVM_ABI bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
LLVM_ABI unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
LLVM_ABI bool hasMultiVectorLoadStore(unsigned NumVectors, MaskSource Mask, VectorType *VectorTy=nullptr, bool IsStore=false, std::optional< Instruction::CastOps > CastHint=std::nullopt) const
Return true if the target supports loading or storing NumVectors contiguous vectors of type VectorTy ...
LLVM_ABI InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getAtomicMemIntrinsicMaxElementSize() const
LLVM_ABI InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index=-1, const Value *Op0=nullptr, const Value *Op1=nullptr, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
LLVM_ABI std::pair< KnownBits, KnownBits > computeKnownBitsAddrSpaceCast(unsigned ToAS, const Value &PtrOp) const
LLVM_ABI bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
LLVM_ABI unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
static LLVM_ABI PartialReductionExtendKind getPartialReductionExtendKind(Instruction *I)
Get the kind of extension that an instruction represents.
LLVM_ABI InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, OperandValueInfo Op1Info={OK_AnyValue, OP_None}, OperandValueInfo Op2Info={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
LLVM_ABI bool shouldConsiderVectorizationRegPressure() const
LLVM_ABI bool enableWritePrefetching() const
LLVM_ABI bool shouldTreatInstructionLikeSelect(const Instruction *I) const
Should the Select Optimization pass treat the given instruction like a select, potentially converting...
LLVM_ABI bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
LLVM_ABI bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
LLVM_ABI InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *DstTy, VectorType *SrcTy, TTI::TargetCostKind CostKind, ArrayRef< int > Mask={}, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args={}, const Instruction *CtxI=nullptr, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
LLVM_ABI bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace) const
Return true is the target supports interleaved access for the given vector type VTy,...
LLVM_ABI unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
LLVM_ABI bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
LLVM_ABI bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
static LLVM_ABI TargetTransformInfo::VectorInstrContext combineVectorInstrContexts(TargetTransformInfo::VectorInstrContext Ctx1, TargetTransformInfo::VectorInstrContext Ctx2)
Combines 2 context hints into a single value.
LLVM_ABI unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
LLVM_ABI InstructionCost getRegisterClassReloadCost(unsigned ClassID, TargetCostKind CostKind) const
LLVM_ABI ReductionShuffle getPreferredExpandedReductionShuffle(const IntrinsicInst *II) const
static LLVM_ABI OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
LLVM_ABI InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
LLVM_ABI InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
LLVM_ABI unsigned getAddressSpaceJoin(unsigned AS1, unsigned AS2) const
Return the most specific common address space containing AS1 and AS2.
LLVM_ABI unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
LLVM_ABI bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr, int64_t ScalableOffset=0) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
LLVM_ABI PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
LLVM_ABI unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
LLVM_ABI bool isElementTypeLegalForScalableVector(Type *Ty) const
LLVM_ABI bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
LLVM_ABI InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of vector reduction intrinsics.
LLVM_ABI unsigned getMaxPrefetchIterationsAhead() const
LLVM_ABI bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
LLVM_ABI ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
LLVM_ABI InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
LLVM_ABI bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
LLVM_ABI InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
LLVM_ABI bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
Return true if the target supports strided load.
LLVM_ABI TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
LLVM_ABI InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, std::optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
LLVM_ABI bool enableSelectOptimize() const
Should the Select Optimization pass be enabled and ran.
LLVM_ABI bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
OperandValueProperties
Additional properties of an operand's values.
LLVM_ABI int getInliningLastCallToStaticBonus() const
LLVM_ABI bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
LLVM_ABI InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
LLVM_ABI unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
LLVM_ABI unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
LLVM_ABI bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
LLVM_ABI bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
LLVM_ABI std::optional< unsigned > getCacheAssociativity(CacheLevel Level) const
LLVM_ABI bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
LLVM_ABI bool isUniform(const Instruction *I, const SmallBitVector &UniformArgs) const
Determine if an instruction with Custom uniformity can be proven uniform based on which operands are ...
LLVM_ABI InstructionCost getMemcpyCost(const Instruction *I) const
LLVM_ABI unsigned adjustInliningThreshold(const CallBase *CB) const
LLVM_ABI bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
LLVM_ABI bool isTargetIntrinsicWithStructReturnOverloadAtField(Intrinsic::ID ID, int RetIdx) const
Identifies if the vector form of the intrinsic that returns a struct is overloaded at the struct elem...
LLVM_ABI unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
LLVM_ABI InstructionCost getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
LLVM_ABI Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
LLVM_ABI InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
LLVM_ABI bool canSaveCmp(Loop *L, CondBrInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
LLVM_ABI unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
LLVM_ABI bool shouldPrefetchAddressSpace(unsigned AS) const
LLVM_ABI InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
LLVM_ABI unsigned getMinVectorRegisterBitWidth() const
LLVM_ABI InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr, TTI::TargetCostKind CostKind) const
LLVM_ABI bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
LLVM_ABI unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
LLVM_ABI bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
It can be advantageous to detach complex constants from their uses to make their generation cheaper.
LLVM_ABI bool hasArmWideBranch(bool Thumb) const
LLVM_ABI const char * getRegisterClassName(unsigned ClassID) const
MaskSource
Enum describing the source/producer of a mask.
LLVM_ABI bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
LLVM_ABI APInt getPriorityMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
LLVM_ABI TargetTransformInfo(std::unique_ptr< const TargetTransformInfoImplBase > Impl)
Construct a TTI object using a type implementing the Concept API below.
LLVM_ABI bool preferInLoopReduction(RecurKind Kind, Type *Ty) const
LLVM_ABI unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
LLVM_ABI bool hasConditionalLoadStoreForType(Type *Ty, bool IsStore) const
LLVM_ABI InstructionCost getMulAccReductionCost(bool IsUnsigned, unsigned RedOpcode, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add/...
LLVM_ABI unsigned getCacheLineSize() const
LLVM_ABI bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
LLVM_ABI InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind, ArrayRef< const Value * > Scalars={}) const
Returns the cost estimation for alternating opcode pattern that can be lowered to a single instructio...
LLVM_ABI bool shouldCopyAttributeWhenOutliningFrom(const Function *Caller, const Attribute &Attr) const
LLVM_ABI APInt getAddrSpaceCastPreservedPtrMask(unsigned SrcAS, unsigned DstAS) const
Returns a mask indicating which bits of a pointer remain unchanged when casting between address space...
LLVM_ABI int getInlinerVectorBonusPercent() const
LLVM_ABI unsigned getEpilogueVectorizationMinVF() const
LLVM_ABI void collectKernelLaunchBounds(const Function &F, SmallVectorImpl< std::pair< StringRef, int64_t > > &LB) const
Collect kernel launch bounds for F into LB.
PopcntSupportKind
Flags indicating the kind of support for population count.
LLVM_ABI bool preferPredicatedReductionSelect() const
LLVM_ABI InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
LLVM_ABI AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
LLVM_ABI bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
llvm::VectorInstrContext VectorInstrContext
LLVM_ABI bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
LLVM_ABI bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
LLVM_ABI unsigned getInliningThresholdMultiplier() const
LLVM_ABI InstructionCost getBranchMispredictPenalty() const
Returns estimated penalty of a branch misprediction in latency.
LLVM_ABI unsigned getNumberOfRegisters(unsigned ClassID) const
LLVM_ABI bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
LLVM_ABI bool supportsScalableVectors() const
LLVM_ABI bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
LLVM_ABI bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
Return true if the target supports masked compress store.
LLVM_ABI std::optional< unsigned > getMinPageSize() const
LLVM_ABI bool preferSLPInstCountCheck() const
LLVM_ABI bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
LLVM_ABI InstructionCost getInsertExtractValueCost(unsigned Opcode, TTI::TargetCostKind CostKind) const
LLVM_ABI bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
LLVM_ABI std::optional< unsigned > getCacheSize(CacheLevel Level) const
LLVM_ABI std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
LLVM_ABI InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args={}, const Instruction *CtxI=nullptr, const TargetLibraryInfo *TLibInfo=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
LLVM_ABI bool isLegalAddScalableImmediate(int64_t Imm) const
Return true if adding the specified scalable immediate is legal, that is the target has add instructi...
LLVM_ABI bool isTargetIntrinsicWithScalarOpAtArg(Intrinsic::ID ID, unsigned ScalarOpdIdx) const
Identifies if the vector form of the intrinsic has a scalar operand.
LLVM_ABI bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
LLVM_ABI bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
LLVM_ABI unsigned getMinTripCountTailFoldingThreshold() const
LLVM_ABI InstructionCost getPartialReductionCost(unsigned Opcode, Type *InputTypeA, Type *InputTypeB, Type *AccumType, ElementCount VF, PartialReductionExtendKind OpAExtend, PartialReductionExtendKind OpBExtend, std::optional< unsigned > BinOp, TTI::TargetCostKind CostKind, std::optional< FastMathFlags > FMF) const
LLVM_ABI InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
LLVM_ABI bool enableScalableVectorization() const
LLVM_ABI bool useFastCCForInternalCall(Function &F) const
Return true if the input function is internal, should use fastcc calling convention.
LLVM_ABI bool isVectorShiftByScalarCheap(Type *Ty) const
Return true if it's significantly cheaper to shift a vector by a uniform scalar than by an amount whi...
LLVM_ABI bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
LLVM_ABI unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
LLVM_ABI bool isLegalMaskedVectorHistogram(Type *AddrType, Type *DataType) const
LLVM_ABI unsigned getGISelRematGlobalCost() const
static LLVM_ABI Instruction::CastOps getOpcodeForPartialReductionExtendKind(PartialReductionExtendKind Kind)
Get the cast opcode for an extension kind.
MemIndexedMode
The type of load/store indexing.
LLVM_ABI bool isLegalMaskedLoad(Type *DataType, Align Alignment, unsigned AddressSpace, MaskKind MaskKind=VariableOrConstantMask) const
Return true if the target supports masked load.
LLVM_ABI InstructionCost getIndexedVectorInstrCostFromEnd(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
LLVM_ABI bool isProfitableToSinkOperands(Instruction *I, SmallVectorImpl< Use * > &Ops, const LoopInfo *LI=nullptr) const
Return true if sinking I's operands to the same basic block as I is profitable, e....
LLVM_ABI bool areInlineCompatible(const Function *Caller, const Function *Callee) const
LLVM_ABI bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
LLVM_ABI InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
LLVM_ABI bool supportsTailCalls() const
If the target supports tail calls.
LLVM_ABI bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
LLVM_ABI bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Query the target whether the specified address space cast from FromAS to ToAS is valid.
LLVM_ABI unsigned getNumberOfParts(Type *Tp) const
AddressingModeKind
Which addressing mode Loop Strength Reduction will try to generate.
LLVM_ABI bool preferLoopExitWithEqualityComparison(const ICmpInst &Cond, const APInt &PostIncExitValue) const
Return true if replacing the relational loop exit comparison Cond with an equality comparison against...
LLVM_ABI InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
LLVM_ABI bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
LLVM_ABI void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, Align SrcAlign, Align DestAlign, std::optional< uint32_t > AtomicCpySize=std::nullopt) const
LLVM_ABI bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
LLVM_ABI bool isTargetIntrinsicWithOverloadTypeAtArg(Intrinsic::ID ID, int OpdIdx) const
Identifies if the vector form of the intrinsic is overloaded on the type of the operand at index OpdI...
static LLVM_ABI VectorInstrContext getVectorInstrContextHint(const Instruction *I)
Calculates a VectorInstrContext from I.
LLVM_ABI InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const PointersChainInfo &Info, Type *AccessTy, const TargetCostKind CostKind) const
Estimate the cost of a chain of pointers (typically pointer operands of a chain of loads or stores wi...
LLVM_ABI bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
LLVM_ABI bool shouldExpandReduction(const IntrinsicInst *II) const
LLVM_ABI InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind, bool ForPoisonSrc=true, ArrayRef< Value * > VL={}, TTI::VectorInstrContext VIC=TTI::VectorInstrContext::None) const
Estimate the overhead of scalarizing an instruction.
LLVM_ABI uint64_t getMaxMemIntrinsicInlineSizeThreshold() const
Returns the maximum memset / memcpy size in bytes that still makes it profitable to inline the call.
LLVM_ABI bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, ArrayRef< const Value * > Scalars={}) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
ShuffleKind
The various kinds of shuffle patterns for vector queries.
LLVM_ABI APInt getFeatureMask(const Function &F) const
Returns a bitmask constructed from the target-features or fmv-features metadata of a function corresp...
LLVM_ABI void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
CastContextHint
Represents a hint about the context in which a cast is used.
@ Masked
The cast is used with a masked load/store.
@ None
The cast is not used with a load/store of any kind.
@ Normal
The cast is used with a normal load/store.
@ GatherScatter
The cast is used with a gather/scatter.
LLVM_ABI InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index, TTI::TargetCostKind CostKind) const
LLVM_ABI InstructionCost getRegisterClassSpillCost(unsigned ClassID, TargetCostKind CostKind) const
OperandValueKind
Additional information about an operand's possible values.
CacheLevel
The possible cache levels.
LLVM_ABI bool preferFixedOverScalableIfEqualCost() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition Type.h:46
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
Definition Type.cpp:299
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition Type.h:363
LLVM_ABI bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
Definition Type.cpp:61
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition Value.h:75
Type * getType() const
All values are typed, get the type of this value.
Definition Value.h:257
Base class of all SIMD vector types.
ElementCount getElementCount() const
Return an ElementCount instance to represent the (possibly scalable) number of elements in the vector...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition TypeSize.h:166
An efficient, type-erasing, non-owning reference to a callable.
CallInst * Call
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
@ Length
Definition DWP.cpp:577
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1755
InstructionCost Cost
@ Known
Known to have no common set bits.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
Definition Casting.h:643
VectorInstrContext
Represents a hint about the context in which a vector instruction or intrinsic is used.
@ None
The instruction is not folded.
@ Load
The value being inserted comes from a load (InsertElement only).
@ Store
The extracted value is stored (ExtractElement only).
LLVM_ABI Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool containsIrreducibleCFG(RPOTraversalT &RPOTraversal, const LoopInfoT &LI)
Return true if the control flow in RPOTraversal is irreducible.
Definition CFG.h:154
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
Definition Casting.h:547
LLVM_ABI ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
RecurKind
These are the kinds of recurrences that we support.
@ Fast
Assign the register banks as fast as possible (default).
constexpr unsigned BitWidth
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition STLExtras.h:1933
constexpr auto seq(T Begin, T End)
Iterate over an integral type from Begin up to - but not including - End.
Definition Sequence.h:341
auto predecessors(const MachineBasicBlock *BB)
AnalysisManager< Function > FunctionAnalysisManager
Convenience typedef for the Function analysis manager.
ValueUniformity
Enum describing how values behave with respect to uniformity and divergence, to answer the question: ...
Definition Uniformity.h:18
@ NeverUniform
The result value can never be assumed to be uniform.
Definition Uniformity.h:26
@ Default
The result value is uniform if and only if all operands are uniform.
Definition Uniformity.h:20
Implement std::hash so that hash_code can be used in STL containers.
Definition BitVector.h:878
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition Alignment.h:39
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition Analysis.h:29
Attributes of a target dependent hardware loop.
LLVM_ABI bool canAnalyze(LoopInfo &LI)
LLVM_ABI bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
OperandValueInfo mergeWith(const OperandValueInfo OpInfoY)
Describe known properties for a set of pointers.
Parameters that control the generic loop unrolling transformation.