LLVM 23.0.0git
SeedCollection.cpp
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1//===- SeedCollection.cpp - Seed collection pass --------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
16
17namespace llvm {
18
20 OverrideVecRegBits("sbvec-vec-reg-bits", cl::init(0), cl::Hidden,
21 cl::desc("Override the vector register size in bits, "
22 "which is otherwise found by querying TTI."));
23static cl::opt<bool>
24 AllowNonPow2("sbvec-allow-non-pow2", cl::init(false), cl::Hidden,
25 cl::desc("Allow non-power-of-2 vectorization."));
26
27#define LoadSeedsDef "loads"
28#define StoreSeedsDef "stores"
30 "sbvec-collect-seeds", cl::init(StoreSeedsDef), cl::Hidden,
31 cl::desc("Collect these seeds. Use empty for none or a comma-separated "
32 "list of '" StoreSeedsDef "' and '" LoadSeedsDef "'."));
33
34namespace sandboxir {
35
37 : FunctionPass("seed-collection"),
38 RPM("rpm", Pipeline, SandboxVectorizerPassBuilder::createRegionPass) {
39 if (!AuxArg.empty()) {
40 if (AuxArg != DiffTypesArgStr) {
41 std::string ErrStr;
42 raw_string_ostream ErrSS(ErrStr);
43 ErrSS << "SeedCollection only supports '" << DiffTypesArgStr
44 << "' aux argument!\n";
45 reportFatalUsageError(ErrStr.c_str());
46 }
47 AllowDiffTypes = true;
48 }
49}
50
52 bool Change = false;
53 const auto &DL = F.getParent()->getDataLayout();
54 bool CollectStores = CollectSeeds.find(StoreSeedsDef) != std::string::npos;
55 bool CollectLoads = CollectSeeds.find(LoadSeedsDef) != std::string::npos;
56
57 // TODO: Start from innermost BBs first
58 for (auto &BB : F) {
59 SeedCollector SC(&BB, A.getScalarEvolution(), CollectStores, CollectLoads,
60 AllowDiffTypes);
61 for (auto &SeedRange : {SC.getStoreSeeds(), SC.getLoadSeeds()}) {
62 for (SeedBundle &Seeds : SeedRange) {
63 unsigned ElmBits =
65 Seeds[Seeds.getFirstUnusedElementIdx()])),
66 DL);
67 unsigned AS = getLoadStoreAddressSpace(Seeds[0]);
68 unsigned VecRegBits = OverrideVecRegBits != 0
70 : A.getTTI().getLoadStoreVecRegBitWidth(AS);
71
72 auto DivideBy2 = [](unsigned Num) {
73 auto Floor = VecUtils::getFloorPowerOf2(Num);
74 if (Floor == Num)
75 return Floor / 2;
76 return Floor;
77 };
78 // Try to create the largest vector supported by the target. If it fails
79 // reduce the vector size by half.
80 for (unsigned SliceElms = std::min(VecRegBits / ElmBits,
81 Seeds.getNumUnusedBits() / ElmBits);
82 SliceElms >= 2u; SliceElms = DivideBy2(SliceElms)) {
83 if (Seeds.allUsed())
84 break;
85 // Keep trying offsets after FirstUnusedElementIdx, until we vectorize
86 // the slice. This could be quite expensive, so we enforce a limit.
87 for (unsigned Offset = Seeds.getFirstUnusedElementIdx(),
88 OE = Seeds.size();
89 Offset + 1 < OE; Offset += 1) {
90 // Seeds are getting used as we vectorize, so skip them.
91 if (Seeds.isUsed(Offset))
92 continue;
93 if (Seeds.allUsed())
94 break;
95
96 auto SeedSlice =
97 Seeds.getSlice(Offset, SliceElms * ElmBits, !AllowNonPow2);
98 if (SeedSlice.empty())
99 continue;
100
101 assert(SeedSlice.size() >= 2 && "Should have been rejected!");
102
103 // Create a region containing the seed slice.
104 auto &Ctx = F.getContext();
105 RegionWithScore Rgn(Ctx, A.getTTI());
106 Rgn.setAux(SeedSlice);
107 // Run the region pass pipeline.
108 Change |= RPM.runOnRegion(Rgn, A);
109 Rgn.clearAux();
110 }
111 }
112 }
113 }
114 }
115 return Change;
116}
117} // namespace sandboxir
118} // namespace llvm
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
#define F(x, y, z)
Definition MD5.cpp:54
#define StoreSeedsDef
#define LoadSeedsDef
This pass exposes codegen information to IR-level passes.
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
constexpr bool empty() const
Check if the string is empty.
Definition StringRef.h:141
FunctionPass(StringRef Name)
Name can't contain any spaces or start with '-'.
Definition Pass.h:78
A Region class that tracks its instructions score.
LLVM_ABI void clearAux()
Clears all auxiliary data.
Definition Region.cpp:75
void setAux(unsigned Idx, Instruction *I)
Set I as the Idx'th element in the auxiliary vector.
Definition Region.cpp:46
A set of candidate Instructions for vectorizing together.
SeedCollection(StringRef Pipeline, StringRef AuxArg)
bool runOnFunction(Function &F, const Analyses &A) final
\Returns true if it modifies F.
iterator_range< SeedContainer::iterator > getLoadSeeds()
iterator_range< SeedContainer::iterator > getStoreSeeds()
static unsigned getNumBits(Type *Ty, const DataLayout &DL)
\Returns the number of bits of Ty.
Definition Utils.h:66
static Type * getExpectedType(const Value *V)
\Returns the expected type of Value V.
Definition Utils.h:32
static Type * getElementType(Type *Ty)
Returns Ty if scalar or its element type if vector.
Definition VecUtils.h:49
static LLVM_ABI unsigned getFloorPowerOf2(unsigned Num)
\Returns the first integer power of 2 that is <= Num.
Definition VecUtils.cpp:13
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
@ Offset
Definition DWP.cpp:558
unsigned getLoadStoreAddressSpace(const Value *I)
A helper function that returns the address space of the pointer operand of load or store instruction.
static cl::opt< unsigned > OverrideVecRegBits("sbvec-vec-reg-bits", cl::init(0), cl::Hidden, cl::desc("Override the vector register size in bits, " "which is otherwise found by querying TTI."))
static cl::opt< bool > AllowNonPow2("sbvec-allow-non-pow2", cl::init(false), cl::Hidden, cl::desc("Allow non-power-of-2 vectorization."))
cl::opt< std::string > CollectSeeds("sbvec-collect-seeds", cl::init(StoreSeedsDef), cl::Hidden, cl::desc("Collect these seeds. Use empty for none or a comma-separated " "list of '" StoreSeedsDef "' and '" LoadSeedsDef "'."))