RegisterClassInfo.h

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//===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file implements the RegisterClassInfo class which provides dynamic
// information about target register classes. Callee saved and reserved
// registers depends on calling conventions and other dynamic information, so
// some things cannot be determined statically.
//
//===----------------------------------------------------------------------===//
 
#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
#define LLVM_CODEGEN_REGISTERCLASSINFO_H
 
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/MC/MCRegister.h"
#include "llvm/Support/Compiler.h"
#include <cstdint>
#include <memory>
 
namespace llvm {
 
class MachineRegisterClassAnalysis;
 
class RegisterClassInfo {
  struct RCInfo {
    unsigned Tag = 0;
    unsigned NumRegs = 0;
    bool ProperSubClass = false;
    uint8_t MinCost = 0;
    uint16_t LastCostChange = 0;
    std::unique_ptr<MCPhysReg[]> Order;
 
    RCInfo() = default;
 
    operator ArrayRef<MCPhysReg>() const {
      return ArrayRef(Order.get(), NumRegs);
    }
  };
 
  // Brief cached information for each register class.
  std::unique_ptr<RCInfo[]> RegClass;
 
  // Tag changes whenever cached information needs to be recomputed. An RCInfo
  // entry is valid when its tag matches.
  unsigned Tag = 0;
 
  bool Reverse = false;
 
  const MachineFunction *MF = nullptr;
  const TargetRegisterInfo *TRI = nullptr;
 
  // Callee saved registers of last MF.
  // Used only to determine if an update for CalleeSavedAliases is necessary.
  SmallVector<MCPhysReg, 16> LastCalleeSavedRegs;
 
  // Map regunit to the callee saved Register.
  SmallVector<MCPhysReg> CalleeSavedAliases;
 
  // Indicate if a specified callee saved register be in the allocation order
  // exactly as written in the tablegen descriptions or listed later.
  BitVector IgnoreCSRForAllocOrder;
 
  // Reserved registers in the current MF.
  BitVector Reserved;
 
  std::unique_ptr<unsigned[]> PSetLimits;
 
  // The register cost values.
  ArrayRef<uint8_t> RegCosts;
 
  // Compute all information about RC.
  LLVM_ABI void compute(const TargetRegisterClass *RC) const;
 
  // Return an up-to-date RCInfo for RC.
  const RCInfo &get(const TargetRegisterClass *RC) const {
    const RCInfo &RCI = RegClass[RC->getID()];
    if (Tag != RCI.Tag)
      compute(RC);
    return RCI;
  }
 
public:
  LLVM_ABI RegisterClassInfo();
 
  /// runOnFunction - Prepare to answer questions about MF. Rev indicates to
  /// use reversed raw order when compute register order. This must be called
  /// before any other methods are used.
  LLVM_ABI void runOnMachineFunction(const MachineFunction &MF,
                                     bool Rev = false);
 
  /// Update cached register class information using ReservedInput, MRI's
  /// current reserved-register set. Cached orders are compacted when
  /// only registers are added and `-stress-regalloc` is disabled; otherwise,
  /// they are invalidated and recomputed on demand.
  ///
  /// RegisterClassInfo must be initialized. Target information, callee-saved
  /// registers, register costs, and allocation orders must remain unchanged.
  LLVM_ABI void updateReservedRegs(const BitVector &ReservedInput);
 
  /// Whether the cached information was filtered by MRI's frozen reserved
  /// registers, i.e. no change to them was left unpublished.
  LLVM_ABI bool hasCurrentReservedRegs() const;
 
  bool invalidate(MachineFunction &, const PreservedAnalyses &PA,
                  MachineFunctionAnalysisManager::Invalidator &) {
    auto PAC = PA.getChecker<MachineRegisterClassAnalysis>();
    return !PAC.preservedWhenStateless();
  }
 
  /// getNumAllocatableRegs - Returns the number of actually allocatable
  /// registers in RC in the current function.
  unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
    return get(RC).NumRegs;
  }
 
  /// getOrder - Returns the preferred allocation order for RC. The order
  /// contains no reserved registers, and registers that alias callee saved
  /// registers come last.
  ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
    return get(RC);
  }
 
  /// isProperSubClass - Returns true if RC has a legal super-class with more
  /// allocatable registers.
  ///
  /// Register classes like GR32_NOSP are not proper sub-classes because %esp
  /// is not allocatable.  Similarly, tGPR is not a proper sub-class in Thumb
  /// mode because the GPR super-class is not legal.
  bool isProperSubClass(const TargetRegisterClass *RC) const {
    return get(RC).ProperSubClass;
  }
 
  /// Return the callee-saved register containing \p Unit, or NoRegister if
  /// there is none.
  MCRegister getCalleeSavedAlias(MCRegUnit Unit) const {
    return CalleeSavedAliases[static_cast<unsigned>(Unit)];
  }
 
  /// getLastCalleeSavedAlias - Returns the last callee saved register that
  /// overlaps PhysReg, or NoRegister if PhysReg doesn't overlap a
  /// CalleeSavedAliases.
  MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const {
    MCRegister CSR;
    for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
      CSR = getCalleeSavedAlias(Unit);
      if (CSR)
        break;
    }
    return CSR;
  }
 
  /// Get the minimum register cost in RC's allocation order.
  /// This is the smallest value in RegCosts[Reg] for all
  /// the registers in getOrder(RC).
  uint8_t getMinCost(const TargetRegisterClass *RC) const {
    return get(RC).MinCost;
  }
 
  /// Get the position of the last cost change in getOrder(RC).
  ///
  /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
  /// same cost according to RegCosts[Reg].
  unsigned getLastCostChange(const TargetRegisterClass *RC) const {
    return get(RC).LastCostChange;
  }
 
  /// Get the register unit limit for the given pressure set index.
  ///
  /// RegisterClassInfo adjusts this limit for reserved registers.
  unsigned getRegPressureSetLimit(unsigned Idx) const {
    if (!PSetLimits[Idx])
      PSetLimits[Idx] = computePSetLimit(Idx);
    return PSetLimits[Idx];
  }
 
protected:
  LLVM_ABI unsigned computePSetLimit(unsigned Idx) const;
};
 
class MachineRegisterClassAnalysis
    : public AnalysisInfoMixin<MachineRegisterClassAnalysis> {
  friend AnalysisInfoMixin<MachineRegisterClassAnalysis>;
 
  static AnalysisKey Key;
 
public:
  using Result = RegisterClassInfo;
 
  LLVM_ABI Result run(MachineFunction &, MachineFunctionAnalysisManager &);
};
 
class LLVM_ABI MachineRegisterClassInfoWrapperPass
    : public MachineFunctionPass {
  virtual void anchor();
 
  RegisterClassInfo RCI;
 
public:
  static char ID;
 
  MachineRegisterClassInfoWrapperPass();
 
  void getAnalysisUsage(AnalysisUsage &AU) const override {
    AU.setPreservesAll();
    MachineFunctionPass::getAnalysisUsage(AU);
  }
 
  bool runOnMachineFunction(MachineFunction &MF) override;
 
  RegisterClassInfo &getRCI() { return RCI; }
  const RegisterClassInfo &getRCI() const { return RCI; }
};
 
} // end namespace llvm
 
#endif // LLVM_CODEGEN_REGISTERCLASSINFO_H