84 if (&Subtarget == &NewSubtarget)
87 Names2InstrOpCodes.clear();
89 Names2RegMasks.clear();
90 Names2SubRegIndices.clear();
91 Names2TargetIndices.clear();
92 Names2DirectTargetFlags.clear();
93 Names2BitmaskTargetFlags.clear();
94 Names2MMOTargetFlags.clear();
96 initNames2RegClasses();
100void PerTargetMIParsingState::initNames2Regs() {
101 if (!Names2Regs.empty())
105 Names2Regs.insert(std::make_pair(
"noreg", 0));
107 assert(
TRI &&
"Expected target register info");
109 for (
unsigned I = 0, E =
TRI->getNumRegs();
I < E; ++
I) {
114 assert(WasInserted &&
"Expected registers to be unique case-insensitively");
121 auto RegInfo = Names2Regs.find(
RegName);
122 if (RegInfo == Names2Regs.end())
124 Reg = RegInfo->getValue();
130 const auto *
TRI = Subtarget.getRegisterInfo();
131 std::optional<uint8_t> FV =
TRI->getVRegFlagValue(FlagName);
138void PerTargetMIParsingState::initNames2InstrOpCodes() {
139 if (!Names2InstrOpCodes.
empty())
142 assert(
TII &&
"Expected target instruction info");
143 for (
unsigned I = 0, E =
TII->getNumOpcodes();
I < E; ++
I)
149 initNames2InstrOpCodes();
150 auto InstrInfo = Names2InstrOpCodes.find(InstrName);
151 if (InstrInfo == Names2InstrOpCodes.end())
153 OpCode = InstrInfo->getValue();
157void PerTargetMIParsingState::initNames2RegMasks() {
158 if (!Names2RegMasks.
empty())
161 assert(
TRI &&
"Expected target register info");
165 for (
size_t I = 0, E = RegMasks.
size();
I < E; ++
I)
167 std::make_pair(
StringRef(RegMaskNames[
I]).lower(), RegMasks[
I]));
171 initNames2RegMasks();
172 auto RegMaskInfo = Names2RegMasks.find(Identifier);
173 if (RegMaskInfo == Names2RegMasks.end())
175 return RegMaskInfo->getValue();
178void PerTargetMIParsingState::initNames2SubRegIndices() {
179 if (!Names2SubRegIndices.
empty())
182 for (
unsigned I = 1, E =
TRI->getNumSubRegIndices();
I < E; ++
I)
183 Names2SubRegIndices.
insert(
184 std::make_pair(
TRI->getSubRegIndexName(
I),
I));
188 initNames2SubRegIndices();
189 auto SubRegInfo = Names2SubRegIndices.find(Name);
190 if (SubRegInfo == Names2SubRegIndices.end())
192 return SubRegInfo->getValue();
195void PerTargetMIParsingState::initNames2TargetIndices() {
196 if (!Names2TargetIndices.
empty())
199 assert(
TII &&
"Expected target instruction info");
200 auto Indices =
TII->getSerializableTargetIndices();
201 for (
const auto &
I : Indices)
206 initNames2TargetIndices();
207 auto IndexInfo = Names2TargetIndices.find(Name);
208 if (IndexInfo == Names2TargetIndices.end())
210 Index = IndexInfo->second;
214void PerTargetMIParsingState::initNames2DirectTargetFlags() {
215 if (!Names2DirectTargetFlags.
empty())
219 assert(
TII &&
"Expected target instruction info");
220 auto Flags =
TII->getSerializableDirectMachineOperandTargetFlags();
221 for (
const auto &
I : Flags)
222 Names2DirectTargetFlags.
insert(
228 initNames2DirectTargetFlags();
229 auto FlagInfo = Names2DirectTargetFlags.find(Name);
230 if (FlagInfo == Names2DirectTargetFlags.end())
232 Flag = FlagInfo->second;
236void PerTargetMIParsingState::initNames2BitmaskTargetFlags() {
237 if (!Names2BitmaskTargetFlags.
empty())
241 assert(
TII &&
"Expected target instruction info");
242 auto Flags =
TII->getSerializableBitmaskMachineOperandTargetFlags();
243 for (
const auto &
I : Flags)
244 Names2BitmaskTargetFlags.
insert(
250 initNames2BitmaskTargetFlags();
251 auto FlagInfo = Names2BitmaskTargetFlags.find(Name);
252 if (FlagInfo == Names2BitmaskTargetFlags.end())
254 Flag = FlagInfo->second;
258void PerTargetMIParsingState::initNames2MMOTargetFlags() {
259 if (!Names2MMOTargetFlags.
empty())
263 assert(
TII &&
"Expected target instruction info");
264 auto Flags =
TII->getSerializableMachineMemOperandTargetFlags();
265 for (
const auto &
I : Flags)
271 initNames2MMOTargetFlags();
272 auto FlagInfo = Names2MMOTargetFlags.find(Name);
273 if (FlagInfo == Names2MMOTargetFlags.end())
275 Flag = FlagInfo->second;
279void PerTargetMIParsingState::initNames2RegClasses() {
280 if (!Names2RegClasses.
empty())
284 for (
unsigned I = 0, E =
TRI->getNumRegClasses();
I < E; ++
I) {
285 const auto *RC =
TRI->getRegClass(
I);
291void PerTargetMIParsingState::initNames2RegBanks() {
292 if (!Names2RegBanks.empty())
295 const RegisterBankInfo *RBI = Subtarget.getRegBankInfo();
303 Names2RegBanks.insert(
304 std::make_pair(StringRef(RegBank.getName()).lower(), &RegBank));
310 auto RegClassInfo = Names2RegClasses.find(Name);
311 if (RegClassInfo == Names2RegClasses.end())
313 return RegClassInfo->getValue();
317 auto RegBankInfo = Names2RegBanks.find(Name);
318 if (RegBankInfo == Names2RegBanks.end())
320 return RegBankInfo->getValue();
334 I.first->second = Info;
336 return *
I.first->second;
345 Info->
VReg =
MF.getRegInfo().createIncompleteVirtualRegister(
RegName);
346 I.first->second = Info;
348 return *
I.first->second;
356 Slots2Values.
insert(std::make_pair(
unsigned(Slot), V));
364 for (
const auto &Arg :
F.args())
366 for (
const auto &BB :
F) {
368 for (
const auto &
I : BB)
383struct ParsedMachineOperand {
387 std::optional<unsigned> TiedDefIdx;
391 std::optional<unsigned> &TiedDefIdx)
392 : Operand(Operand), Begin(Begin), End(End), TiedDefIdx(TiedDefIdx) {
395 "Only used register operands can be tied");
402 StringRef
Source, CurrentSource;
405 PerFunctionMIParsingState &PFS;
407 DenseMap<unsigned, const BasicBlock *> Slots2BasicBlocks;
410 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
412 MIParser(PerFunctionMIParsingState &PFS, SMDiagnostic &
Error,
413 StringRef Source, SMRange SourceRange);
417 void lex(
unsigned SkipChar = 0);
422 bool error(
const Twine &Msg);
430 parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
431 bool parseBasicBlocks();
433 bool parseStandaloneMBB(MachineBasicBlock *&
MBB);
435 bool parseStandaloneVirtualRegister(VRegInfo *&Info);
437 bool parseStandaloneStackObject(
int &FI);
438 bool parseStandaloneMDNode(MDNode *&Node);
440 bool parseMDTuple(MDNode *&MD,
bool IsDistinct);
441 bool parseMDNodeVector(SmallVectorImpl<Metadata *> &Elts);
445 parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
446 bool parseBasicBlock(MachineBasicBlock &
MBB,
447 MachineBasicBlock *&AddFalthroughFrom);
448 bool parseBasicBlockLiveins(MachineBasicBlock &
MBB);
449 bool parseBasicBlockSuccessors(MachineBasicBlock &
MBB);
452 bool parseVirtualRegister(VRegInfo *&Info);
453 bool parseNamedVirtualRegister(VRegInfo *&Info);
454 bool parseRegister(
Register &
Reg, VRegInfo *&VRegInfo);
455 bool parseRegisterFlag(
RegState &Flags);
456 bool parseRegisterClassOrBank(VRegInfo &RegInfo);
457 bool parseSubRegisterIndex(
unsigned &SubReg);
458 bool parseRegisterTiedDefIndex(
unsigned &TiedDefIdx);
459 bool parseRegisterOperand(MachineOperand &Dest,
460 std::optional<unsigned> &TiedDefIdx,
462 bool parseImmediateOperand(MachineOperand &Dest);
467 bool parseTypedImmediateOperand(MachineOperand &Dest);
468 bool parseFPImmediateOperand(MachineOperand &Dest);
470 bool parseMBBOperand(MachineOperand &Dest);
471 bool parseStackFrameIndex(
int &FI);
472 bool parseStackObjectOperand(MachineOperand &Dest);
473 bool parseFixedStackFrameIndex(
int &FI);
474 bool parseFixedStackObjectOperand(MachineOperand &Dest);
476 bool parseGlobalAddressOperand(MachineOperand &Dest);
477 bool parseConstantPoolIndexOperand(MachineOperand &Dest);
478 bool parseSubRegisterIndexOperand(MachineOperand &Dest);
479 bool parseJumpTableIndexOperand(MachineOperand &Dest);
480 bool parseExternalSymbolOperand(MachineOperand &Dest);
481 bool parseMCSymbolOperand(MachineOperand &Dest);
483 bool parseDIExpression(MDNode *&Expr);
484 bool parseDILocation(MDNode *&Expr);
485 bool parseMetadataOperand(MachineOperand &Dest);
486 bool parseCFIOffset(
int &
Offset);
487 bool parseCFIRegister(
unsigned &
Reg);
489 bool parseCFIEscapeValues(std::string& Values);
490 bool parseCFIOperand(MachineOperand &Dest);
491 bool parseIRBlock(BasicBlock *&BB,
const Function &
F);
492 bool parseBlockAddressOperand(MachineOperand &Dest);
493 bool parseIntrinsicOperand(MachineOperand &Dest);
494 bool parsePredicateOperand(MachineOperand &Dest);
495 bool parseShuffleMaskOperand(MachineOperand &Dest);
496 bool parseTargetIndexOperand(MachineOperand &Dest);
497 bool parseDbgInstrRefOperand(MachineOperand &Dest);
498 bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
499 bool parseLaneMaskOperand(MachineOperand &Dest);
500 bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
501 bool parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
502 MachineOperand &Dest,
503 std::optional<unsigned> &TiedDefIdx);
504 bool parseMachineOperandAndTargetFlags(
const unsigned OpCode,
505 const unsigned OpIdx,
506 MachineOperand &Dest,
507 std::optional<unsigned> &TiedDefIdx);
508 bool parseOffset(int64_t &
Offset);
509 bool parseIRBlockAddressTaken(BasicBlock *&BB);
511 bool parseAddrspace(
unsigned &Addrspace);
512 bool parseSectionID(std::optional<MBBSectionID> &SID);
513 bool parseBBID(std::optional<UniqueBBID> &BBID);
514 bool parseCallFrameSize(
unsigned &CallFrameSize);
516 bool parseOperandsOffset(MachineOperand &
Op);
519 bool parseMemoryPseudoSourceValue(
const PseudoSourceValue *&PSV);
520 bool parseMachinePointerInfo(MachinePointerInfo &Dest);
523 bool parseMachineMemoryOperand(MachineMemOperand *&Dest);
524 bool parsePreOrPostInstrSymbol(MCSymbol *&Symbol);
525 bool parseHeapAllocMarker(MDNode *&Node);
526 bool parsePCSections(MDNode *&Node);
527 bool parseMMRA(MDNode *&Node);
529 bool parseTargetImmMnemonic(
const unsigned OpCode,
const unsigned OpIdx,
530 MachineOperand &Dest,
const MIRFormatter &MF);
541 bool getUint64(uint64_t &Result);
557 bool parseInstruction(
unsigned &OpCode,
unsigned &Flags);
559 bool assignRegisterTies(MachineInstr &
MI,
563 const MCInstrDesc &MCID);
566 const BasicBlock *getIRBlock(
unsigned Slot,
const Function &
F);
569 MCSymbol *getOrCreateMCSymbol(StringRef Name);
573 bool parseStringConstant(std::string &Result);
590 SourceRange(SourceRange), PFS(PFS) {}
592void MIParser::lex(
unsigned SkipChar) {
594 CurrentSource.substr(SkipChar), Token,
598bool MIParser::error(
const Twine &Msg) {
return error(Token.location(), Msg); }
618 assert(SourceRange.isValid() &&
"Invalid source range");
640 return "<unknown token>";
645 if (Token.isNot(TokenKind))
652 if (Token.isNot(TokenKind))
659bool MIParser::parseSectionID(std::optional<MBBSectionID> &SID) {
665 return error(
"Unknown Section ID");
668 const StringRef &S = Token.stringValue();
669 if (S ==
"Exception")
671 else if (S ==
"Cold")
674 return error(
"Unknown Section ID");
681bool MIParser::parseBBID(std::optional<UniqueBBID> &BBID) {
683 return error(
"expected 'bb_id'");
686 unsigned CloneID = 0;
689 auto Parts = S.
split(
'.');
690 if (Parts.first.getAsInteger(10, BaseID) ||
691 Parts.second.getAsInteger(10, CloneID))
692 return error(
"Unknown BB ID");
696 return error(
"Unknown BB ID");
701 return error(
"Unknown Clone ID");
705 return error(
"Unknown Clone ID");
709 BBID = {BaseID, CloneID};
714bool MIParser::parseCallFrameSize(
unsigned &CallFrameSize) {
719 return error(
"Unknown call frame size");
720 CallFrameSize =
Value;
727 std::optional<UniqueBBID> BBID;
736bool MIParser::parseBasicBlockDefinition(
742 auto Loc = Token.location();
743 auto Name = Token.stringValue();
745 bool MachineBlockAddressTaken =
false;
747 bool IsLandingPad =
false;
748 bool IsInlineAsmBrIndirectTarget =
false;
749 bool IsEHFuncletEntry =
false;
750 bool IsEHScopeEntry =
false;
751 std::optional<MBBSectionID> SectionID;
752 uint64_t Alignment = 0;
753 std::optional<UniqueBBID> BBID;
754 unsigned CallFrameSize = 0;
759 switch (Token.kind()) {
761 MachineBlockAddressTaken =
true;
765 if (parseIRBlockAddressTaken(AddressTakenIRBlock))
773 IsInlineAsmBrIndirectTarget =
true;
777 IsEHFuncletEntry =
true;
781 IsEHScopeEntry =
true;
791 if (parseIRBlock(BB, MF.getFunction()))
796 if (parseSectionID(SectionID))
804 if (parseCallFrameSize(CallFrameSize))
819 MF.getFunction().getValueSymbolTable()->lookup(Name));
822 "' is not defined in the function '" +
825 auto *
MBB = MF.CreateMachineBasicBlock(BB, BBID);
827 bool WasInserted = MBBSlots.
insert(std::make_pair(
ID,
MBB)).second;
829 return error(
Loc,
Twine(
"redefinition of machine basic block with id #") +
833 if (MachineBlockAddressTaken)
835 if (AddressTakenIRBlock)
849bool MIParser::parseBasicBlockDefinitions(
855 if (Token.isErrorOrEOF())
856 return Token.isError();
858 return error(
"expected a basic block definition before instructions");
859 unsigned BraceDepth = 0;
861 if (parseBasicBlockDefinition(MBBSlots))
863 bool IsAfterNewline =
false;
867 Token.isErrorOrEOF())
870 return error(
"basic block definition should be located at the start of "
873 IsAfterNewline =
true;
876 IsAfterNewline =
false;
881 return error(
"extraneous closing brace ('}')");
887 if (!Token.isError() && BraceDepth)
888 return error(
"expected '}'");
889 }
while (!Token.isErrorOrEOF());
890 return Token.isError();
898 if (Token.isNewlineOrEOF())
902 return error(
"expected a named register");
904 if (parseNamedRegister(
Reg))
912 return error(
"expected a lane mask");
914 "Use correct get-function for lane mask");
917 return error(
"invalid lane mask value");
931 if (Token.isNewlineOrEOF())
935 return error(
"expected a machine basic block reference");
944 return error(
"expected an integer literal after '('");
978 bool ExplicitSuccessors =
false;
981 if (parseBasicBlockSuccessors(
MBB))
983 ExplicitSuccessors =
true;
985 if (parseBasicBlockLiveins(
MBB))
992 if (!Token.isNewlineOrEOF())
993 return error(
"expected line break at the end of a list");
998 bool IsInBundle =
false;
1022 return error(
"nested instruction bundles are not allowed");
1031 assert(Token.isNewlineOrEOF() &&
"MI is not fully parsed");
1036 if (!ExplicitSuccessors) {
1043 if (IsFallthrough) {
1044 AddFalthroughFrom = &
MBB;
1053bool MIParser::parseBasicBlocks() {
1058 if (Token.isErrorOrEOF())
1059 return Token.isError();
1068 if (AddFalthroughFrom) {
1072 AddFalthroughFrom =
nullptr;
1074 if (parseBasicBlock(*
MBB, AddFalthroughFrom))
1087 while (Token.isRegister() || Token.isRegisterFlag()) {
1088 auto Loc = Token.location();
1089 std::optional<unsigned> TiedDefIdx;
1090 if (parseRegisterOperand(MO, TiedDefIdx,
true))
1093 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1102 if (Token.isError() || parseInstruction(OpCode, Flags))
1115 auto Loc = Token.location();
1116 std::optional<unsigned> TiedDefIdx;
1117 if (parseMachineOperandAndTargetFlags(OpCode, Operands.
size(), MO, TiedDefIdx))
1120 ParsedMachineOperand(MO,
Loc, Token.location(), TiedDefIdx));
1125 return error(
"expected ',' before the next machine operand");
1129 MCSymbol *PreInstrSymbol =
nullptr;
1131 if (parsePreOrPostInstrSymbol(PreInstrSymbol))
1133 MCSymbol *PostInstrSymbol =
nullptr;
1135 if (parsePreOrPostInstrSymbol(PostInstrSymbol))
1137 MDNode *HeapAllocMarker =
nullptr;
1139 if (parseHeapAllocMarker(HeapAllocMarker))
1141 MDNode *PCSections =
nullptr;
1143 if (parsePCSections(PCSections))
1148 unsigned CFIType = 0;
1152 return error(
"expected an integer literal after 'cfi-type'");
1170 unsigned InstrNum = 0;
1174 return error(
"expected an integer literal after 'debug-instr-number'");
1191 if (parseDILocation(Node))
1194 return error(
"expected a metadata node after 'debug-location'");
1197 return error(
"referenced metadata is not a DILocation");
1205 while (!Token.isNewlineOrEOF()) {
1207 if (parseMachineMemoryOperand(
MemOp))
1210 if (Token.isNewlineOrEOF())
1215 return error(
"expected ',' before the next machine memory operand");
1220 const auto &
MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
1221 if (!
MCID.isVariadic()) {
1223 if (verifyImplicitOperands(Operands,
MCID))
1227 MI = MF.CreateMachineInstr(
MCID, DebugLocation,
true);
1228 MI->setFlags(Flags);
1232 for (
const auto &Operand : Operands)
1233 MI->addOperand(MF, Operand.Operand);
1235 if (assignRegisterTies(*
MI, Operands))
1238 MI->setPreInstrSymbol(MF, PreInstrSymbol);
1239 if (PostInstrSymbol)
1240 MI->setPostInstrSymbol(MF, PostInstrSymbol);
1241 if (HeapAllocMarker)
1242 MI->setHeapAllocMarker(MF, HeapAllocMarker);
1244 MI->setPCSections(MF, PCSections);
1246 MI->setMMRAMetadata(MF, MMRA);
1248 MI->setCFIType(MF, CFIType);
1250 MI->setDeactivationSymbol(MF, DS);
1251 if (!MemOperands.
empty())
1252 MI->setMemRefs(MF, MemOperands);
1254 MI->setDebugInstrNum(InstrNum);
1261 return error(
"expected a machine basic block reference");
1267 "expected end of string after the machine basic block reference");
1271bool MIParser::parseStandaloneNamedRegister(
Register &
Reg) {
1274 return error(
"expected a named register");
1275 if (parseNamedRegister(
Reg))
1279 return error(
"expected end of string after the register reference");
1283bool MIParser::parseStandaloneVirtualRegister(
VRegInfo *&Info) {
1286 return error(
"expected a virtual register");
1287 if (parseVirtualRegister(Info))
1291 return error(
"expected end of string after the register reference");
1295bool MIParser::parseStandaloneRegister(
Register &
Reg) {
1299 return error(
"expected either a named or virtual register");
1302 if (parseRegister(
Reg, Info))
1307 return error(
"expected end of string after the register reference");
1311bool MIParser::parseStandaloneStackObject(
int &FI) {
1314 return error(
"expected a stack object");
1315 if (parseStackFrameIndex(FI))
1318 return error(
"expected end of string after the stack object reference");
1322bool MIParser::parseStandaloneMDNode(
MDNode *&Node) {
1328 if (parseDIExpression(Node))
1331 if (parseDILocation(Node))
1334 return error(
"expected a metadata node");
1337 return error(
"expected end of string after the metadata node");
1341bool MIParser::parseMachineMetadata() {
1344 return error(
"expected a metadata node");
1348 return error(
"expected metadata id after '!'");
1359 return error(
"expected a metadata node");
1363 if (parseMDTuple(MD, IsDistinct))
1366 auto FI = PFS.MachineForwardRefMDNodes.find(
ID);
1367 if (FI != PFS.MachineForwardRefMDNodes.end()) {
1368 FI->second.first->replaceAllUsesWith(MD);
1369 PFS.MachineForwardRefMDNodes.erase(FI);
1371 assert(PFS.MachineMetadataNodes[
ID] == MD &&
"Tracking VH didn't work");
1373 auto [It,
Inserted] = PFS.MachineMetadataNodes.try_emplace(
ID);
1375 return error(
"Metadata id is already used");
1376 It->second.reset(MD);
1382bool MIParser::parseMDTuple(
MDNode *&MD,
bool IsDistinct) {
1384 if (parseMDNodeVector(Elts))
1393 return error(
"expected '{' here");
1414 return error(
"expected end of metadata node");
1422bool MIParser::parseMetadata(
Metadata *&MD) {
1424 return error(
"expected '!' here");
1429 if (parseStringConstant(Str))
1436 return error(
"expected metadata id after '!'");
1438 SMLoc Loc = mapSMLoc(Token.location());
1445 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
1446 if (NodeInfo != PFS.IRSlots.MetadataNodes.end()) {
1447 MD = NodeInfo->second.get();
1451 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
1452 if (NodeInfo != PFS.MachineMetadataNodes.end()) {
1453 MD = NodeInfo->second.get();
1457 auto &FwdRef = PFS.MachineForwardRefMDNodes[
ID];
1458 FwdRef = std::make_pair(
1460 PFS.MachineMetadataNodes[
ID].reset(FwdRef.first.get());
1461 MD = FwdRef.first.get();
1468 return MO.
isDef() ?
"implicit-def" :
"implicit";
1473 assert(
Reg.isPhysical() &&
"expected phys reg");
1480 for (
const auto &
I : Operands) {
1501 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
1502 assert(
TRI &&
"Expected target register info");
1503 for (
const auto &
I : ImplicitOperands) {
1506 return error(Operands.
empty() ? Token.location() : Operands.
back().End,
1507 Twine(
"missing implicit register operand '") +
1514bool MIParser::parseInstruction(
unsigned &OpCode,
unsigned &Flags) {
1583 return error(
"expected a machine instruction");
1584 StringRef InstrName = Token.stringValue();
1585 if (PFS.Target.parseInstrName(InstrName, OpCode))
1586 return error(
Twine(
"unknown machine instruction name '") + InstrName +
"'");
1594 if (PFS.Target.getRegisterByName(Name,
Reg))
1595 return error(
Twine(
"unknown register name '") + Name +
"'");
1599bool MIParser::parseNamedVirtualRegister(
VRegInfo *&Info) {
1604 Info = &PFS.getVRegInfoNamed(Name);
1608bool MIParser::parseVirtualRegister(
VRegInfo *&Info) {
1610 return parseNamedVirtualRegister(Info);
1615 Info = &PFS.getVRegInfo(
ID);
1620 switch (Token.kind()) {
1625 return parseNamedRegister(
Reg);
1628 if (parseVirtualRegister(Info))
1638bool MIParser::parseRegisterClassOrBank(
VRegInfo &RegInfo) {
1640 return error(
"expected '_', register class, or register bank name");
1649 switch (RegInfo.
Kind) {
1655 return error(
Loc,
Twine(
"conflicting register classes, previously: ") +
1664 return error(
Loc,
"register class specification on generic register");
1672 RegBank = PFS.Target.getRegBank(Name);
1674 return error(
Loc,
"expected '_', register class, or register bank name");
1679 switch (RegInfo.
Kind) {
1685 return error(
Loc,
"conflicting generic register banks");
1691 return error(
Loc,
"register bank specification on normal register");
1696bool MIParser::parseRegisterFlag(
RegState &Flags) {
1698 switch (Token.kind()) {
1732 if (OldFlags == Flags)
1735 return error(
"duplicate '" + Token.stringValue() +
"' register flag");
1740bool MIParser::parseSubRegisterIndex(
unsigned &SubReg) {
1744 return error(
"expected a subregister index after '.'");
1745 auto Name = Token.stringValue();
1746 SubReg = PFS.Target.getSubRegIndex(Name);
1748 return error(
Twine(
"use of unknown subregister index '") + Name +
"'");
1753bool MIParser::parseRegisterTiedDefIndex(
unsigned &TiedDefIdx) {
1757 return error(
"expected an integer literal after 'tied-def'");
1767 for (
unsigned I = 0,
E = Operands.
size();
I !=
E; ++
I) {
1768 if (!Operands[
I].TiedDefIdx)
1772 unsigned DefIdx = *Operands[
I].TiedDefIdx;
1774 return error(Operands[
I].Begin,
1775 Twine(
"use of invalid tied-def operand index '" +
1776 Twine(DefIdx) +
"'; instruction has only ") +
1778 const auto &DefOperand = Operands[DefIdx].Operand;
1779 if (!DefOperand.isReg() || !DefOperand.isDef())
1781 return error(Operands[
I].Begin,
1782 Twine(
"use of invalid tied-def operand index '") +
1783 Twine(DefIdx) +
"'; the operand #" +
Twine(DefIdx) +
1784 " isn't a defined register");
1786 for (
const auto &TiedPair : TiedRegisterPairs) {
1787 if (TiedPair.first == DefIdx)
1788 return error(Operands[
I].Begin,
1789 Twine(
"the tied-def operand #") +
Twine(DefIdx) +
1790 " is already tied with another register operand");
1792 TiedRegisterPairs.push_back(std::make_pair(DefIdx,
I));
1796 for (
const auto &TiedPair : TiedRegisterPairs)
1797 MI.tieOperands(TiedPair.first, TiedPair.second);
1802 std::optional<unsigned> &TiedDefIdx,
1805 while (Token.isRegisterFlag()) {
1806 if (parseRegisterFlag(Flags))
1811 if (!Token.isRegister())
1812 return error(
"expected a register after register flags");
1815 if (parseRegister(
Reg, RegInfo))
1818 unsigned SubReg = 0;
1820 if (parseSubRegisterIndex(SubReg))
1823 return error(
"subregister index expects a virtual register");
1827 return error(
"register class specification expects a virtual register");
1829 if (parseRegisterClassOrBank(*RegInfo))
1838 return error(
"tied-def not supported for defs");
1840 if (parseRegisterTiedDefIndex(Idx))
1845 return error(
"unexpected type on physical register");
1849 if (parseLowLevelType(Token.location(), Ty))
1851 :
error(
"expected tied-def or low-level type after '('");
1858 return error(
"inconsistent type for generic virtual register");
1868 return error(
"generic virtual registers must have a type");
1873 return error(
"cannot have a killed def operand");
1876 return error(
"cannot have a dead use operand");
1893 const APSInt &
Int = Token.integerValue();
1894 if (
auto SImm =
Int.trySExtValue();
Int.isSigned() && SImm.has_value())
1896 else if (
auto UImm =
Int.tryZExtValue(); !
Int.isSigned() && UImm.has_value())
1899 return error(
"integer literal is too large to be an immediate operand");
1904bool MIParser::parseTargetImmMnemonic(
const unsigned OpCode,
1905 const unsigned OpIdx,
1909 auto Loc = Token.location();
1915 Len += Token.range().size();
1924 Src =
StringRef(
Loc, Len + Token.stringValue().size());
1929 ->
bool { return error(Loc, Msg); }))
1941 auto Source = StringValue.
str();
1946 return ErrCB(
Loc + Err.getColumnNo(), Err.getMessage());
1952 return ::parseIRConstant(
1953 Loc, StringValue, PFS,
C,
1980 if (Token.range().front() ==
's' || Token.range().front() ==
'p') {
1983 return error(
"expected integers after 's'/'p' type character");
1986 if (Token.range().front() ==
's') {
1990 return error(
"invalid size for scalar type");
1997 }
else if (Token.range().front() ==
'p') {
2001 return error(
"invalid address space number");
2010 return error(
Loc,
"expected sN, pA, <M x sN>, <M x pA>, <vscale x M x sN>, "
2011 "or <vscale x M x pA> for GlobalISel type");
2019 return error(
"expected <vscale x M x sN> or <vscale x M x pA>");
2023 auto GetError = [
this, &HasVScale,
Loc]() {
2026 Loc,
"expected <vscale x M x sN> or <vscale M x pA> for vector type");
2027 return error(
Loc,
"expected <M x sN> or <M x pA> for vector type");
2032 uint64_t NumElements = Token.integerValue().getZExtValue();
2034 return error(
"invalid number of vector elements");
2042 if (Token.range().front() !=
's' && Token.range().front() !=
'p')
2047 return error(
"expected integers after 's'/'p' type character");
2049 if (Token.range().front() ==
's') {
2052 return error(
"invalid size for scalar element in vector");
2054 }
else if (Token.range().front() ==
'p') {
2058 return error(
"invalid address space number");
2078 if (TypeStr.
front() !=
'i' && TypeStr.
front() !=
's' &&
2079 TypeStr.
front() !=
'p')
2081 "a typed immediate operand should start with one of 'i', 's', or 'p'");
2084 return error(
"expected integers after 'i'/'s'/'p' type character");
2086 auto Loc = Token.location();
2090 !(Token.range() ==
"true" || Token.range() ==
"false"))
2091 return error(
"expected an integer literal");
2101 auto Loc = Token.location();
2105 return error(
"expected a floating point literal");
2116 assert(S[0] ==
'0' && tolower(S[1]) ==
'x');
2118 if (!isxdigit(S[2]))
2121 APInt A(V.size()*4, V, 16);
2125 unsigned NumBits = (
A == 0) ? 32 :
A.getActiveBits();
2136 return ErrCB(Token.
location(),
"expected unsigned integer");
2139 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2147 if (
A.getBitWidth() > 32)
2148 return ErrCB(Token.
location(),
"expected 32-bit integer (too large)");
2149 Result =
A.getZExtValue();
2155bool MIParser::getUnsigned(
unsigned &Result) {
2156 return ::getUnsigned(
2168 auto MBBInfo = PFS.MBBSlots.find(
Number);
2169 if (MBBInfo == PFS.MBBSlots.end())
2170 return error(
Twine(
"use of undefined machine basic block #") +
2172 MBB = MBBInfo->second;
2175 if (!Token.stringValue().empty() && Token.stringValue() !=
MBB->
getName())
2177 " isn't '" + Token.stringValue() +
"'");
2190bool MIParser::parseStackFrameIndex(
int &FI) {
2195 auto ObjectInfo = PFS.StackObjectSlots.find(
ID);
2196 if (ObjectInfo == PFS.StackObjectSlots.end())
2200 if (
const auto *Alloca =
2201 MF.getFrameInfo().getObjectAllocation(ObjectInfo->second))
2202 Name = Alloca->getName();
2203 if (!Token.stringValue().empty() && Token.stringValue() != Name)
2205 "' isn't '" + Token.stringValue() +
"'");
2207 FI = ObjectInfo->second;
2213 if (parseStackFrameIndex(FI))
2219bool MIParser::parseFixedStackFrameIndex(
int &FI) {
2224 auto ObjectInfo = PFS.FixedStackObjectSlots.find(
ID);
2225 if (ObjectInfo == PFS.FixedStackObjectSlots.end())
2226 return error(
Twine(
"use of undefined fixed stack object '%fixed-stack.") +
2229 FI = ObjectInfo->second;
2233bool MIParser::parseFixedStackObjectOperand(
MachineOperand &Dest) {
2235 if (parseFixedStackFrameIndex(FI))
2244 switch (Token.
kind()) {
2249 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '") +
2250 Token.
range() +
"'");
2259 return ErrCB(Token.
location(),
Twine(
"use of undefined global value '@") +
2260 Twine(GVIdx) +
"'");
2269bool MIParser::parseGlobalValue(
GlobalValue *&GV) {
2270 return ::parseGlobalValue(
2283 if (parseOperandsOffset(Dest))
2288bool MIParser::parseConstantPoolIndexOperand(
MachineOperand &Dest) {
2295 return error(
"use of undefined constant '%const." +
Twine(
ID) +
"'");
2298 if (parseOperandsOffset(Dest))
2308 auto JumpTableEntryInfo = PFS.JumpTableSlots.find(
ID);
2309 if (JumpTableEntryInfo == PFS.JumpTableSlots.end())
2310 return error(
"use of undefined jump table '%jump-table." +
Twine(
ID) +
"'");
2318 const char *
Symbol = MF.createExternalSymbolName(Token.stringValue());
2321 if (parseOperandsOffset(Dest))
2331 if (parseOperandsOffset(Dest))
2336bool MIParser::parseSubRegisterIndexOperand(
MachineOperand &Dest) {
2339 unsigned SubRegIndex = PFS.Target.getSubRegIndex(Token.stringValue());
2340 if (SubRegIndex == 0)
2341 return error(
Twine(
"unknown subregister index '") + Name +
"'");
2347bool MIParser::parseMDNode(
MDNode *&Node) {
2350 auto Loc = Token.location();
2353 return error(
"expected metadata id after '!'");
2357 auto NodeInfo = PFS.IRSlots.MetadataNodes.find(
ID);
2358 if (NodeInfo == PFS.IRSlots.MetadataNodes.end()) {
2359 NodeInfo = PFS.MachineMetadataNodes.find(
ID);
2360 if (NodeInfo == PFS.MachineMetadataNodes.end())
2364 Node = NodeInfo->second.get();
2368bool MIParser::parseDIExpression(
MDNode *&Expr) {
2371 CurrentSource,
Read,
Error, *PFS.MF.getFunction().getParent(),
2373 CurrentSource = CurrentSource.substr(
Read);
2380bool MIParser::parseDILocation(
MDNode *&
Loc) {
2384 bool HaveLine =
false;
2386 unsigned Column = 0;
2388 MDNode *InlinedAt =
nullptr;
2389 bool ImplicitCode =
false;
2390 uint64_t AtomGroup = 0;
2391 uint64_t AtomRank = 0;
2399 if (Token.stringValue() ==
"line") {
2404 Token.integerValue().isSigned())
2405 return error(
"expected unsigned integer");
2406 Line = Token.integerValue().getZExtValue();
2411 if (Token.stringValue() ==
"column") {
2416 Token.integerValue().isSigned())
2417 return error(
"expected unsigned integer");
2418 Column = Token.integerValue().getZExtValue();
2422 if (Token.stringValue() ==
"scope") {
2427 return error(
"expected metadata node");
2429 return error(
"expected DIScope node");
2432 if (Token.stringValue() ==
"inlinedAt") {
2440 if (parseDILocation(InlinedAt))
2443 return error(
"expected metadata node");
2446 return error(
"expected DILocation node");
2449 if (Token.stringValue() ==
"isImplicitCode") {
2454 return error(
"expected true/false");
2458 if (Token.stringValue() ==
"true")
2459 ImplicitCode =
true;
2460 else if (Token.stringValue() ==
"false")
2461 ImplicitCode =
false;
2463 return error(
"expected true/false");
2467 if (Token.stringValue() ==
"atomGroup") {
2472 Token.integerValue().isSigned())
2473 return error(
"expected unsigned integer");
2474 AtomGroup = Token.integerValue().getZExtValue();
2478 if (Token.stringValue() ==
"atomRank") {
2483 Token.integerValue().isSigned())
2484 return error(
"expected unsigned integer");
2485 AtomRank = Token.integerValue().getZExtValue();
2490 return error(
Twine(
"invalid DILocation argument '") +
2491 Token.stringValue() +
"'");
2499 return error(
"DILocation requires line number");
2501 return error(
"DILocation requires a scope");
2504 InlinedAt, ImplicitCode, AtomGroup, AtomRank);
2514 if (parseDIExpression(Node))
2521bool MIParser::parseCFIOffset(
int &
Offset) {
2523 return error(
"expected a cfi offset");
2524 if (Token.integerValue().getSignificantBits() > 32)
2525 return error(
"expected a 32 bit integer (the cfi offset is too large)");
2526 Offset = (int)Token.integerValue().getExtValue();
2531bool MIParser::parseCFIRegister(
unsigned &
Reg) {
2533 return error(
"expected a cfi register");
2535 if (parseNamedRegister(LLVMReg))
2537 const auto *
TRI = MF.getSubtarget().getRegisterInfo();
2538 assert(
TRI &&
"Expected target register info");
2539 int DwarfReg =
TRI->getDwarfRegNum(LLVMReg,
true);
2541 return error(
"invalid DWARF register");
2542 Reg = (unsigned)DwarfReg;
2547bool MIParser::parseCFIAddressSpace(
unsigned &
AddressSpace) {
2549 return error(
"expected a cfi address space literal");
2550 if (Token.integerValue().isSigned())
2551 return error(
"expected an unsigned integer (cfi address space)");
2557bool MIParser::parseCFIEscapeValues(std::string &Values) {
2560 return error(
"expected a hexadecimal literal");
2564 if (
Value > UINT8_MAX)
2565 return error(
"expected a 8-bit integer (too large)");
2566 Values.push_back(
static_cast<uint8_t
>(
Value));
2573 auto Kind = Token.kind();
2581 if (parseCFIRegister(
Reg))
2596 CFIIndex = MF.addFrameInst(
2600 if (parseCFIRegister(
Reg))
2606 if (parseCFIOffset(
Offset))
2612 if (parseCFIOffset(
Offset))
2614 CFIIndex = MF.addFrameInst(
2636 if (parseCFIRegister(
Reg))
2644 if (parseCFIRegister(
Reg))
2651 parseCFIRegister(Reg2))
2670 if (parseCFIEscapeValues(Values))
2684 switch (Token.kind()) {
2687 F.getValueSymbolTable()->lookup(Token.stringValue()));
2689 return error(
Twine(
"use of undefined IR block '") + Token.range() +
"'");
2693 unsigned SlotNumber = 0;
2696 BB =
const_cast<BasicBlock *
>(getIRBlock(SlotNumber,
F));
2698 return error(
Twine(
"use of undefined IR block '%ir-block.") +
2699 Twine(SlotNumber) +
"'");
2715 return error(
"expected a global value");
2721 return error(
"expected an IR function reference");
2727 return error(
"expected an IR block reference");
2728 if (parseIRBlock(BB, *
F))
2734 if (parseOperandsOffset(Dest))
2743 return error(
"expected syntax intrinsic(@llvm.whatever)");
2746 return error(
"expected syntax intrinsic(@llvm.whatever)");
2748 std::string
Name = std::string(Token.stringValue());
2752 return error(
"expected ')' to terminate intrinsic name");
2757 return error(
"unknown intrinsic name");
2769 return error(
"expected syntax intpred(whatever) or floatpred(whatever");
2772 return error(
"whatever");
2795 return error(
"invalid floating-point predicate");
2810 return error(
"invalid integer predicate");
2816 return error(
"predicate should be terminated by ')'.");
2826 return error(
"expected syntax shufflemask(<integer or undef>, ...)");
2833 const APSInt &
Int = Token.integerValue();
2836 return error(
"expected integer constant");
2843 return error(
"shufflemask should be terminated by ')'.");
2845 if (ShufMask.
size() < 2)
2846 return error(
"shufflemask should have > 1 element");
2858 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2861 return error(
"expected unsigned integer for instruction index");
2862 uint64_t InstrIdx = Token.integerValue().getZExtValue();
2863 assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
2864 "Instruction reference's instruction index is too large");
2868 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2871 return error(
"expected unsigned integer for operand index");
2872 uint64_t
OpIdx = Token.integerValue().getZExtValue();
2873 assert(
OpIdx <= std::numeric_limits<unsigned>::max() &&
2874 "Instruction reference's operand index is too large");
2878 return error(
"expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
2890 return error(
"expected the name of the target index");
2892 if (PFS.Target.getTargetIndex(Token.stringValue(), Index))
2893 return error(
"use of undefined target index '" + Token.stringValue() +
"'");
2898 if (parseOperandsOffset(Dest))
2903bool MIParser::parseCustomRegisterMaskOperand(
MachineOperand &Dest) {
2904 assert(Token.stringValue() ==
"CustomRegMask" &&
"Expected a custom RegMask");
2909 uint32_t *
Mask = MF.allocateRegMask();
2913 return error(
"expected a named register");
2915 if (parseNamedRegister(
Reg))
2939 return error(
"expected a valid lane mask value");
2941 "Use correct get-function for lane mask.");
2955bool MIParser::parseLiveoutRegisterMaskOperand(
MachineOperand &Dest) {
2957 uint32_t *
Mask = MF.allocateRegMask();
2963 return error(
"expected a named register");
2965 if (parseNamedRegister(
Reg))
2980bool MIParser::parseMachineOperand(
const unsigned OpCode,
const unsigned OpIdx,
2982 std::optional<unsigned> &TiedDefIdx) {
2983 switch (Token.kind()) {
2998 return parseRegisterOperand(Dest, TiedDefIdx);
3000 return parseImmediateOperand(Dest);
3008 return parseFPImmediateOperand(Dest);
3010 return parseMBBOperand(Dest);
3012 return parseStackObjectOperand(Dest);
3014 return parseFixedStackObjectOperand(Dest);
3017 return parseGlobalAddressOperand(Dest);
3019 return parseConstantPoolIndexOperand(Dest);
3021 return parseJumpTableIndexOperand(Dest);
3023 return parseExternalSymbolOperand(Dest);
3025 return parseMCSymbolOperand(Dest);
3027 return parseSubRegisterIndexOperand(Dest);
3030 return parseMetadataOperand(Dest);
3048 return parseCFIOperand(Dest);
3050 return parseBlockAddressOperand(Dest);
3052 return parseIntrinsicOperand(Dest);
3054 return parseTargetIndexOperand(Dest);
3056 return parseLaneMaskOperand(Dest);
3058 return parseLiveoutRegisterMaskOperand(Dest);
3061 return parsePredicateOperand(Dest);
3063 return parseShuffleMaskOperand(Dest);
3065 return parseDbgInstrRefOperand(Dest);
3069 if (
const auto *RegMask = PFS.Target.getRegMask(Token.stringValue())) {
3073 }
else if (Token.stringValue() ==
"CustomRegMask") {
3074 return parseCustomRegisterMaskOperand(Dest);
3076 return parseTypedImmediateOperand(Dest);
3079 const auto *
TII = MF.getSubtarget().getInstrInfo();
3080 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3081 return parseTargetImmMnemonic(OpCode,
OpIdx, Dest, *Formatter);
3087 return error(
"expected a machine operand");
3092bool MIParser::parseMachineOperandAndTargetFlags(
3094 std::optional<unsigned> &TiedDefIdx) {
3096 bool HasTargetFlags =
false;
3098 HasTargetFlags =
true;
3103 return error(
"expected the name of the target flag");
3104 if (PFS.Target.getDirectTargetFlag(Token.stringValue(), TF)) {
3105 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), TF))
3106 return error(
"use of undefined target flag '" + Token.stringValue() +
3113 return error(
"expected the name of the target flag");
3114 unsigned BitFlag = 0;
3115 if (PFS.Target.getBitmaskTargetFlag(Token.stringValue(), BitFlag))
3116 return error(
"use of undefined target flag '" + Token.stringValue() +
3125 auto Loc = Token.location();
3126 if (parseMachineOperand(OpCode,
OpIdx, Dest, TiedDefIdx))
3128 if (!HasTargetFlags)
3131 return error(
Loc,
"register operands can't have target flags");
3136bool MIParser::parseOffset(int64_t &
Offset) {
3143 return error(
"expected an integer literal after '" + Sign +
"'");
3144 if (Token.integerValue().getSignificantBits() > 64)
3145 return error(
"expected 64-bit integer (too large)");
3146 Offset = Token.integerValue().getExtValue();
3153bool MIParser::parseIRBlockAddressTaken(
BasicBlock *&BB) {
3157 return error(
"expected basic block after 'ir_block_address_taken'");
3159 if (parseIRBlock(BB, MF.getFunction()))
3166bool MIParser::parseAlignment(uint64_t &Alignment) {
3170 return error(
"expected an integer literal after 'align'");
3171 if (getUint64(Alignment))
3176 return error(
"expected a power-of-2 literal after 'align'");
3181bool MIParser::parseAddrspace(
unsigned &Addrspace) {
3185 return error(
"expected an integer literal after 'addrspace'");
3202 switch (Token.
kind()) {
3208 unsigned SlotNumber = 0;
3236 return ErrCB(Token.
location(),
Twine(
"use of undefined IR value '") + Token.
range() +
"'");
3240bool MIParser::parseIRValue(
const Value *&V) {
3241 return ::parseIRValue(
3247bool MIParser::getUint64(uint64_t &Result) {
3248 if (Token.hasIntegerValue()) {
3249 if (Token.integerValue().getActiveBits() > 64)
3250 return error(
"expected 64-bit integer (too large)");
3251 Result = Token.integerValue().getZExtValue();
3258 if (
A.getBitWidth() > 64)
3259 return error(
"expected 64-bit integer (too large)");
3266bool MIParser::getHexUint(
APInt &Result) {
3267 return ::getHexUint(Token, Result);
3271 const auto OldFlags =
Flags;
3272 switch (Token.kind()) {
3287 if (PFS.Target.getMMOTargetFlag(Token.stringValue(), TF))
3288 return error(
"use of undefined target MMO flag '" + Token.stringValue() +
3296 if (OldFlags == Flags)
3299 return error(
"duplicate '" + Token.stringValue() +
"' memory operand flag");
3305 switch (Token.kind()) {
3307 PSV = MF.getPSVManager().getStack();
3310 PSV = MF.getPSVManager().getGOT();
3313 PSV = MF.getPSVManager().getJumpTable();
3316 PSV = MF.getPSVManager().getConstantPool();
3320 if (parseFixedStackFrameIndex(FI))
3322 PSV = MF.getPSVManager().getFixedStack(FI);
3328 if (parseStackFrameIndex(FI))
3330 PSV = MF.getPSVManager().getFixedStack(FI);
3336 switch (Token.kind()) {
3342 PSV = MF.getPSVManager().getGlobalValueCallEntry(GV);
3346 PSV = MF.getPSVManager().getExternalSymbolCallEntry(
3347 MF.createExternalSymbolName(Token.stringValue()));
3351 "expected a global value or an external symbol after 'call-entry'");
3356 const auto *
TII = MF.getSubtarget().getInstrInfo();
3357 if (
const auto *Formatter =
TII->getMIRFormatter()) {
3358 if (Formatter->parseCustomPseudoSourceValue(
3359 Token.stringValue(), MF, PFS, PSV,
3361 return error(Loc, Msg);
3365 return error(
"unable to parse target custom pseudo source value");
3382 if (parseMemoryPseudoSourceValue(PSV))
3395 return error(
"expected an IR value reference");
3396 const Value *
V =
nullptr;
3399 if (V && !
V->getType()->isPointerTy())
3400 return error(
"expected a pointer IR value");
3415 return error(
"expected '(' in syncscope");
3418 if (parseStringConstant(SSN))
3421 SSID =
Context.getOrInsertSyncScopeID(SSN);
3423 return error(
"expected ')' in syncscope");
3429bool MIParser::parseOptionalAtomicOrdering(
AtomicOrdering &Order) {
3448 return error(
"expected an atomic scope, ordering or a size specification");
3455 while (Token.isMemoryOperandFlag()) {
3456 if (parseMemoryOperandFlag(Flags))
3460 (Token.stringValue() !=
"load" && Token.stringValue() !=
"store"))
3461 return error(
"expected 'load' or 'store' memory operation");
3462 if (Token.stringValue() ==
"load")
3476 if (parseOptionalScope(MF.getFunction().getContext(), SSID))
3481 if (parseOptionalAtomicOrdering(Order))
3484 if (parseOptionalAtomicOrdering(FailureOrder))
3490 return error(
"expected memory LLT, the size integer literal or 'unknown-size' after "
3491 "memory operation");
3496 if (getUint64(
Size))
3507 if (parseLowLevelType(Token.location(), MemoryType))
3520 if (Token.stringValue() != Word)
3521 return error(
Twine(
"expected '") + Word +
"'");
3524 if (parseMachinePointerInfo(Ptr))
3527 uint64_t BaseAlignment =
3534 switch (Token.kind()) {
3540 if (Ptr.
Offset & (Alignment - 1)) {
3545 return error(
"specified alignment is more aligned than offset");
3547 BaseAlignment = Alignment;
3586 return error(
"expected 'align' or '!tbaa' or '!alias.scope' or "
3587 "'!noalias' or '!range' or '!noalias.addrspace'");
3592 Dest = MF.getMachineMemOperand(Ptr, Flags, MemoryType,
Align(BaseAlignment),
3593 AAInfo,
Range, SSID, Order, FailureOrder);
3597bool MIParser::parsePreOrPostInstrSymbol(
MCSymbol *&Symbol) {
3600 "Invalid token for a pre- post-instruction symbol!");
3603 return error(
"expected a symbol after 'pre-instr-symbol'");
3604 Symbol = getOrCreateMCSymbol(Token.stringValue());
3610 return error(
"expected ',' before the next machine operand");
3615bool MIParser::parseHeapAllocMarker(
MDNode *&Node) {
3617 "Invalid token for a heap alloc marker!");
3622 return error(
"expected a MDNode after 'heap-alloc-marker'");
3627 return error(
"expected ',' before the next machine operand");
3632bool MIParser::parsePCSections(
MDNode *&Node) {
3634 "Invalid token for a PC sections!");
3639 return error(
"expected a MDNode after 'pcsections'");
3644 return error(
"expected ',' before the next machine operand");
3649bool MIParser::parseMMRA(
MDNode *&Node) {
3658 return error(
"expected ',' before the next machine operand");
3668 for (
const auto &BB :
F) {
3674 Slots2BasicBlocks.
insert(std::make_pair(
unsigned(Slot), &BB));
3681 return Slots2BasicBlocks.
lookup(Slot);
3684const BasicBlock *MIParser::getIRBlock(
unsigned Slot) {
3685 if (Slots2BasicBlocks.empty())
3691 if (&
F == &MF.getFunction())
3692 return getIRBlock(Slot);
3704 return MF.getContext().getOrCreateSymbol(Name);
3707bool MIParser::parseStringConstant(std::string &Result) {
3709 return error(
"expected string constant");
3710 Result = std::string(Token.stringValue());
3718 return MIParser(PFS,
Error, Src).parseBasicBlockDefinitions(PFS.
MBBSlots);
3723 return MIParser(PFS,
Error, Src).parseBasicBlocks();
3729 return MIParser(PFS,
Error, Src).parseStandaloneMBB(
MBB);
3735 return MIParser(PFS,
Error, Src).parseStandaloneRegister(Reg);
3741 return MIParser(PFS,
Error, Src).parseStandaloneNamedRegister(Reg);
3747 return MIParser(PFS,
Error, Src).parseStandaloneVirtualRegister(Info);
3752 return MIParser(PFS,
Error, Src).parseStandaloneStackObject(FI);
3758 return MIParser(PFS,
Error, Src).parsePrefetchTarget(
Target);
3762 return MIParser(PFS,
Error, Src).parseStandaloneMDNode(
Node);
3767 return MIParser(PFS,
Error, Src, SrcRange).parseMachineMetadata();
3775 ErrorCallback(
Loc, Msg);
3779 return ::parseIRValue(Token, PFS, V, ErrorCallback);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file defines the StringMap class.
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
This file contains the declarations for the subclasses of Constant, which represent the different fla...
static Error parseAlignment(StringRef Str, Align &Alignment, StringRef Name, bool AllowZero=false)
Attempts to parse an alignment component of a specification.
This file defines the DenseMap class.
const HexagonInstrInfo * TII
Module.h This file contains the declarations for the Module class.
A common definition of LaneBitmask for use in TableGen and CodeGen.
static llvm::Error parse(DataExtractor &Data, uint64_t BaseAddr, LineEntryCallback const &Callback)
Implement a low-level type suitable for MachineInstr level instruction selection.
static const char * printImplicitRegisterFlag(const MachineOperand &MO)
static const BasicBlock * getIRBlockFromSlot(unsigned Slot, const DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
static std::string getRegisterName(const TargetRegisterInfo *TRI, Register Reg)
static bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue, PerFunctionMIParsingState &PFS, const Constant *&C, ErrorCallbackType ErrCB)
static void initSlots2Values(const Function &F, DenseMap< unsigned, const Value * > &Slots2Values)
Creates the mapping from slot numbers to function's unnamed IR values.
static bool parseIRValue(const MIToken &Token, PerFunctionMIParsingState &PFS, const Value *&V, ErrorCallbackType ErrCB)
static bool verifyScalarSize(uint64_t Size)
static bool getUnsigned(const MIToken &Token, unsigned &Result, ErrorCallbackType ErrCB)
static bool getHexUint(const MIToken &Token, APInt &Result)
static bool verifyVectorElementCount(uint64_t NumElts)
static void mapValueToSlot(const Value *V, ModuleSlotTracker &MST, DenseMap< unsigned, const Value * > &Slots2Values)
static void initSlots2BasicBlocks(const Function &F, DenseMap< unsigned, const BasicBlock * > &Slots2BasicBlocks)
function_ref< bool(StringRef::iterator Loc, const Twine &)> ErrorCallbackType
static bool isImplicitOperandIn(const MachineOperand &ImplicitOperand, ArrayRef< ParsedMachineOperand > Operands)
Return true if the parsed machine operands contain a given machine operand.
static bool parseGlobalValue(const MIToken &Token, PerFunctionMIParsingState &PFS, GlobalValue *&GV, ErrorCallbackType ErrCB)
static bool verifyAddrSpace(uint64_t AddrSpace)
Register const TargetRegisterInfo * TRI
Promote Memory to Register
MachineInstr unsigned OpIdx
static constexpr unsigned SM(unsigned Version)
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
static bool parseMetadata(const StringRef &Input, uint64_t &FunctionHash, uint32_t &Attributes)
Parse Input that contains metadata.
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
An arbitrary precision integer that knows its signedness.
bool isNegative() const
Determine sign of this APSInt.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const T & back() const
back - Get the last element.
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
LLVM Basic Block Representation.
static LLVM_ABI BlockAddress * get(Function *F, BasicBlock *BB)
Return a BlockAddress for the specified function and basic block.
static BranchProbability getRaw(uint32_t N)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
static bool isFPPredicate(Predicate P)
static bool isIntPredicate(Predicate P)
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Lightweight error class with error context and mandatory checking.
ValueSymbolTable * getValueSymbolTable()
getSymbolTable() - Return the symbol table if any, otherwise nullptr.
Module * getParent()
Get the module that this global value is contained inside of...
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT token()
Get a low-level token; just a scalar with zero bits (or no size).
This is an important class for using LLVM in a threaded context.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_def_cfa_register modifies a rule for computing CFA.
static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_undefined From now on the previous value of Register can't be restored anymore.
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
static MCCFIInstruction createLLVMDefAspaceCfa(MCSymbol *L, unsigned Register, int64_t Offset, unsigned AddressSpace, SMLoc Loc)
.cfi_llvm_def_aspace_cfa defines the rule for computing the CFA to be the result of evaluating the DW...
static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, unsigned Register2, SMLoc Loc={})
.cfi_register Previous value of Register1 is saved in register Register2.
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
static MCCFIInstruction createNegateRAStateWithPC(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state_with_pc AArch64 negate RA state with PC.
static MCCFIInstruction createNegateRAState(MCSymbol *L, SMLoc Loc={})
.cfi_negate_ra_state AArch64 negate RA state.
static MCCFIInstruction createRememberState(MCSymbol *L, SMLoc Loc={})
.cfi_remember_state Save all current rules for all registers.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int64_t Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
static MCCFIInstruction createWindowSave(MCSymbol *L, SMLoc Loc={})
.cfi_window_save SPARC register window is saved.
static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int64_t Adjustment, SMLoc Loc={})
.cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but Offset is a relative value that is added/subt...
static MCCFIInstruction createRestoreState(MCSymbol *L, SMLoc Loc={})
.cfi_restore_state Restore the previously saved state.
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_same_value Current value of Register is the same as in the previous frame.
static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})
.cfi_rel_offset Previous value of Register is saved at offset Offset from the current CFA register.
Describe properties that are true of each instruction in the target description file.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static LLVM_ABI MDString * get(LLVMContext &Context, StringRef Str)
static MDTuple * getDistinct(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a distinct node.
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
static TempMDTuple getTemporary(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Return a temporary node.
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
void setCallFrameSize(unsigned N)
Set the call frame size on entry to this basic block.
void setAlignment(Align A)
Set alignment of the basic block.
LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void setSectionID(MBBSectionID V)
Sets the section ID for this basic block.
void setIsInlineAsmBrIndirectTarget(bool V=true)
Indicates if this is the indirect dest of an INLINEASM_BR.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
LLVM_ABI bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
LLVM_ABI StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
void setFlag(MIFlag Flag)
Set a MI flag.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateMCSymbol(MCSymbol *Sym, unsigned TargetFlags=0)
static MachineOperand CreateES(const char *SymName, unsigned TargetFlags=0)
static MachineOperand CreateFPImm(const ConstantFP *CFP)
static MachineOperand CreateCFIIndex(unsigned CFIIndex)
static MachineOperand CreateRegMask(const uint32_t *Mask)
CreateRegMask - Creates a register mask operand referencing Mask.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
static MachineOperand CreateCImm(const ConstantInt *CI)
static MachineOperand CreateMetadata(const MDNode *Meta)
static MachineOperand CreatePredicate(unsigned Pred)
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateShuffleMask(ArrayRef< int > Mask)
static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags=0)
static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx)
static MachineOperand CreateRegLiveOut(const uint32_t *Mask)
static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
void setTargetFlags(unsigned F)
static MachineOperand CreateLaneMask(LaneBitmask LaneMask)
LLVM_ABI bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateCPI(unsigned Idx, int Offset, unsigned TargetFlags=0)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, unsigned TargetFlags=0)
static MachineOperand CreateMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0)
static MachineOperand CreateIntrinsicID(Intrinsic::ID ID)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
LLVM_ABI Register createIncompleteVirtualRegister(StringRef Name="")
Creates a new virtual register that has no register class, register bank or size assigned yet.
LLVM_ABI void setType(Register VReg, LLT Ty)
Set the low-level type of VReg to Ty.
void noteNewVirtualRegister(Register Reg)
This interface provides simple read-only access to a block of memory, and provides simple methods for...
virtual StringRef getBufferIdentifier() const
Return an identifier for this buffer, typically the filename it was read from.
const char * getBufferEnd() const
const char * getBufferStart() const
Manage lifetime of a slot tracker for printing IR.
int getLocalSlot(const Value *V)
Return the slot number of the specified local value.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
Special value supplied for machine level alias analysis.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getNumRegBanks() const
Get the total number of register banks.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
constexpr unsigned id() const
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
Represents a range in source code.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This owns the files read by a parser, handles include stacks, and handles diagnostic wrangling.
bool insert(MapEntryTy *KeyValue)
insert - Insert the specified key/value pair into the map.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
std::string str() const
str - Get the contents as an std::string.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
StringRef drop_front(size_t N=1) const
Return a StringRef equal to 'this' but with the first N elements dropped.
constexpr size_t size() const
size - Get the string size.
char front() const
front - Get the first character in the string.
LLVM_ABI std::string lower() const
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const =0
Return the target's register information.
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM_ABI std::string str() const
Return the twine contents as a std::string.
Value * lookup(StringRef Name) const
This method finds the value with the given Name in the the symbol table.
LLVM Value Representation.
An efficient, type-erasing, non-owning reference to a callable.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ BasicBlock
Various leaf nodes.
LLVM_ABI ID lookupIntrinsicID(StringRef Name)
This does the actual lookup of an intrinsic ID which matches the given function name.
@ System
Synchronized with respect to all concurrently executing threads.
support::ulittle32_t Word
Scope
Defines the scope in which this symbol should be visible: Default – Visible in the public interface o...
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
bool parseStackObjectReference(PerFunctionMIParsingState &PFS, int &FI, StringRef Src, SMDiagnostic &Error)
bool parseMDNode(PerFunctionMIParsingState &PFS, MDNode *&Node, StringRef Src, SMDiagnostic &Error)
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
RegState
Flags to represent properties of register accesses.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Kill
The last use of a register.
@ InternalRead
Register reads a value that is defined inside the same instruction or bundle.
@ Undef
Value of the register doesn't matter.
@ EarlyClobber
Register definition happens before uses.
@ Define
Register definition.
@ Renamable
Register that may be renamed.
@ Debug
Register 'use' is for debugging purpose.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
StringRef lexMIToken(StringRef Source, MIToken &Token, function_ref< void(StringRef::iterator, const Twine &)> ErrorCallback)
Consume a single machine instruction token in the given source and return the remaining source string...
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
bool parseMachineBasicBlockDefinitions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine basic block definitions, and skip the machine instructions.
bool parsePrefetchTarget(PerFunctionMIParsingState &PFS, CallsiteID &Target, StringRef Src, SMDiagnostic &Error)
LLVM_ABI void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl< MachineBasicBlock * > &Result, bool &IsFallthrough)
Determine a possible list of successors of a basic block based on the basic block machine operand bei...
bool parseMBBReference(PerFunctionMIParsingState &PFS, MachineBasicBlock *&MBB, StringRef Src, SMDiagnostic &Error)
uint64_t PowerOf2Ceil(uint64_t A)
Returns the power of two which is greater than or equal to the given value.
auto dyn_cast_or_null(const Y &Val)
LLVM_ABI DIExpression * parseDIExpressionBodyAtBeginning(StringRef Asm, unsigned &Read, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots)
constexpr RegState getDefRegState(bool B)
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
constexpr bool hasRegState(RegState Value, RegState Test)
AtomicOrdering
Atomic ordering for LLVM's memory model.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
ArrayRef(const T &OneElt) -> ArrayRef< T >
std::string toString(const APInt &I, unsigned Radix, bool Signed, bool formatAsCLiteral=false, bool UpperCase=true, bool InsertSeparators=false)
bool parseMachineInstructions(PerFunctionMIParsingState &PFS, StringRef Src, SMDiagnostic &Error)
Parse the machine instructions.
bool parseRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
LLVM_ABI Constant * parseConstantValue(StringRef Asm, SMDiagnostic &Err, const Module &M, const SlotMapping *Slots=nullptr)
Parse a type and a constant value in the given string.
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
bool parseMachineMetadata(PerFunctionMIParsingState &PFS, StringRef Src, SMRange SourceRange, SMDiagnostic &Error)
bool parseVirtualRegisterReference(PerFunctionMIParsingState &PFS, VRegInfo *&Info, StringRef Src, SMDiagnostic &Error)
bool parseNamedRegisterReference(PerFunctionMIParsingState &PFS, Register &Reg, StringRef Src, SMDiagnostic &Error)
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * NoAliasAddrSpace
The tag specifying the noalias address spaces.
MDNode * Scope
The tag for alias scope specification (used with noalias).
MDNode * TBAA
The tag for type-based alias analysis.
MDNode * NoAlias
The tag specifying the noalias scope.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static constexpr LaneBitmask getAll()
LLVM_ABI static const MBBSectionID ExceptionSectionID
LLVM_ABI static const MBBSectionID ColdSectionID
A token produced by the machine instruction lexer.
bool hasIntegerValue() const
bool is(TokenKind K) const
StringRef stringValue() const
Return the token's string value.
@ kw_cfi_aarch64_negate_ra_sign_state
@ kw_cfi_llvm_def_aspace_cfa
@ kw_inlineasm_br_indirect_target
@ kw_cfi_aarch64_negate_ra_sign_state_with_pc
@ kw_cfi_def_cfa_register
@ kw_cfi_adjust_cfa_offset
@ kw_machine_block_address_taken
@ kw_ir_block_address_taken
StringRef::iterator location() const
const APSInt & integerValue() const
This class contains a discriminated union of information about pointers in memory operands,...
int64_t Offset
Offset - This is an offset from the base Value*.
VRegInfo & getVRegInfo(Register Num)
const SlotMapping & IRSlots
const Value * getIRValue(unsigned Slot)
DenseMap< unsigned, MachineBasicBlock * > MBBSlots
StringMap< VRegInfo * > VRegInfosNamed
DenseMap< unsigned, const Value * > Slots2Values
Maps from slot numbers to function's unnamed values.
PerFunctionMIParsingState(MachineFunction &MF, SourceMgr &SM, const SlotMapping &IRSlots, PerTargetMIParsingState &Target)
PerTargetMIParsingState & Target
DenseMap< Register, VRegInfo * > VRegInfos
VRegInfo & getVRegInfoNamed(StringRef RegName)
BumpPtrAllocator Allocator
bool getVRegFlagValue(StringRef FlagName, uint8_t &FlagValue) const
bool getDirectTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a direct target flag to the corresponding target flag.
const RegisterBank * getRegBank(StringRef Name)
Check if the given identifier is a name of a register bank.
bool parseInstrName(StringRef InstrName, unsigned &OpCode)
Try to convert an instruction name to an opcode.
unsigned getSubRegIndex(StringRef Name)
Check if the given identifier is a name of a subregister index.
bool getTargetIndex(StringRef Name, int &Index)
Try to convert a name of target index to the corresponding target index.
void setTarget(const TargetSubtargetInfo &NewSubtarget)
bool getRegisterByName(StringRef RegName, Register &Reg)
Try to convert a register name to a register number.
bool getMMOTargetFlag(StringRef Name, MachineMemOperand::Flags &Flag)
Try to convert a name of a MachineMemOperand target flag to the corresponding target flag.
bool getBitmaskTargetFlag(StringRef Name, unsigned &Flag)
Try to convert a name of a bitmask target flag to the corresponding target flag.
const TargetRegisterClass * getRegClass(StringRef Name)
Check if the given identifier is a name of a register class.
const uint32_t * getRegMask(StringRef Identifier)
Check if the given identifier is a name of a register mask.
This struct contains the mappings from the slot numbers to unnamed metadata nodes,...
NumberedValues< GlobalValue * > GlobalValues
const RegisterBank * RegBank
union llvm::VRegInfo::@127225073067155374133234315364317264041071000132 D
const TargetRegisterClass * RC
enum llvm::VRegInfo::@374354327266250320012227113300214031244227062232 Kind
bool Explicit
VReg was explicitly specified in the .mir file.