LLVM 24.0.0git
AVRExpandPseudoInsts.cpp
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1//===-- AVRExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions. This pass should be run after register allocation but before
11// the post-regalloc scheduling pass.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AVR.h"
16#include "AVRInstrInfo.h"
17#include "AVRMachineFunctionInfo.h"
18#include "AVRTargetMachine.h"
19#include "MCTargetDesc/AVRMCTargetDesc.h"
20#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
21#include "llvm/CodeGen/MachineFunctionPass.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachinePassManager.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/TargetRegisterInfo.h"
26#include "llvm/IR/Analysis.h"
27#include "llvm/Pass.h"
28
29using namespace llvm;
30
31#define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
32
33namespace {
34
35/// Expands "placeholder" instructions marked as pseudo into
36/// actual AVR instructions.
37class AVRExpandPseudoLegacy : public MachineFunctionPass {
38public:
39 static char ID;
40
41 AVRExpandPseudoLegacy() : MachineFunctionPass(ID) {}
42
43 bool runOnMachineFunction(MachineFunction &MF) override;
44
45 StringRef getPassName() const override { return AVR_EXPAND_PSEUDO_NAME; }
46
47 void getAnalysisUsage(AnalysisUsage &AU) const override {
48 AU.setPreservesCFG();
49 MachineFunctionPass::getAnalysisUsage(AU);
50 }
51};
52
53class AVRExpandPseudoImpl {
54 typedef MachineBasicBlock Block;
55 typedef Block::iterator BlockIt;
56
57 const AVRRegisterInfo *TRI;
58 const TargetInstrInfo *TII;
59
60 bool expandMBB(Block &MBB);
61 bool expandMI(Block &MBB, BlockIt MBBI);
62 template <unsigned OP> bool expand(Block &MBB, BlockIt MBBI);
63
64 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
65 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
66 }
67
68 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
69 Register DstReg) {
70 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
71 }
72
73 MachineRegisterInfo &getRegInfo(Block &MBB) {
74 return MBB.getParent()->getRegInfo();
75 }
76
77 bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
78 bool expandLogic(unsigned Op, Block &MBB, BlockIt MBBI);
79 bool expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI);
80 bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
81 bool isLogicRegOpUndef(unsigned Op, unsigned ImmVal) const;
82
83 template <typename Func> bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
84
85 template <typename Func>
86 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI, Func f);
87
88 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
89
90 /// Specific shift implementation for int8.
91 bool expandLSLB7Rd(Block &MBB, BlockIt MBBI);
92 bool expandLSRB7Rd(Block &MBB, BlockIt MBBI);
93 bool expandASRB6Rd(Block &MBB, BlockIt MBBI);
94 bool expandASRB7Rd(Block &MBB, BlockIt MBBI);
95
96 /// Specific shift implementation for int16.
97 bool expandLSLW4Rd(Block &MBB, BlockIt MBBI);
98 bool expandLSRW4Rd(Block &MBB, BlockIt MBBI);
99 bool expandASRW7Rd(Block &MBB, BlockIt MBBI);
100 bool expandLSLW8Rd(Block &MBB, BlockIt MBBI);
101 bool expandLSRW8Rd(Block &MBB, BlockIt MBBI);
102 bool expandASRW8Rd(Block &MBB, BlockIt MBBI);
103 bool expandLSLW12Rd(Block &MBB, BlockIt MBBI);
104 bool expandLSRW12Rd(Block &MBB, BlockIt MBBI);
105 bool expandASRW14Rd(Block &MBB, BlockIt MBBI);
106 bool expandASRW15Rd(Block &MBB, BlockIt MBBI);
107
108 // Common implementation of LPMWRdZ and ELPMWRdZ.
109 bool expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsELPM);
110 // Common implementation of LPMBRdZ and ELPMBRdZ.
111 bool expandLPMBELPMB(Block &MBB, BlockIt MBBI, bool IsELPM);
112 // Common implementation of ROLBRdR1 and ROLBRdR17.
113 bool expandROLBRd(Block &MBB, BlockIt MBBI);
114
115public:
116 bool runOnMachineFunction(MachineFunction &MF);
117};
118
119char AVRExpandPseudoLegacy::ID = 0;
120
121bool AVRExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
122 bool Modified = false;
123
124 BlockIt MBBI = MBB.begin(), E = MBB.end();
125 while (MBBI != E) {
126 BlockIt NMBBI = std::next(MBBI);
127 Modified |= expandMI(MBB, MBBI);
128 MBBI = NMBBI;
129 }
130
131 return Modified;
132}
133
134bool AVRExpandPseudoImpl::runOnMachineFunction(MachineFunction &MF) {
135 bool Modified = false;
136
137 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
138 TRI = STI.getRegisterInfo();
139 TII = STI.getInstrInfo();
140
141 for (Block &MBB : MF) {
142 bool ContinueExpanding = true;
143 unsigned ExpandCount = 0;
144
145 // Continue expanding the block until all pseudos are expanded.
146 do {
147 assert(ExpandCount < 10 && "pseudo expand limit reached");
148 (void)ExpandCount;
149
150 bool BlockModified = expandMBB(MBB);
151 Modified |= BlockModified;
152 ExpandCount++;
153
154 ContinueExpanding = BlockModified;
155 } while (ContinueExpanding);
156 }
157
158 return Modified;
159}
160
161bool AVRExpandPseudoImpl::expandArith(unsigned OpLo, unsigned OpHi, Block &MBB,
162 BlockIt MBBI) {
163 MachineInstr &MI = *MBBI;
164 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
165 Register DstReg = MI.getOperand(0).getReg();
166 Register SrcReg = MI.getOperand(2).getReg();
167 bool DstIsDead = MI.getOperand(0).isDead();
168 bool DstIsKill = MI.getOperand(1).isKill();
169 bool SrcIsKill = MI.getOperand(2).isKill();
170 bool ImpIsDead = MI.getOperand(3).isDead();
171 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
172 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
173
174 buildMI(MBB, MBBI, OpLo)
175 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
176 .addReg(DstLoReg, getKillRegState(DstIsKill))
177 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
178
179 auto MIBHI =
180 buildMI(MBB, MBBI, OpHi)
181 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
182 .addReg(DstHiReg, getKillRegState(DstIsKill))
183 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
184
185 if (ImpIsDead)
186 MIBHI->getOperand(3).setIsDead();
187
188 // SREG is always implicitly killed
189 MIBHI->getOperand(4).setIsKill();
190
191 MI.eraseFromParent();
192 return true;
193}
194
195bool AVRExpandPseudoImpl::expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
196 MachineInstr &MI = *MBBI;
197 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
198 Register DstReg = MI.getOperand(0).getReg();
199 Register SrcReg = MI.getOperand(2).getReg();
200 bool DstIsDead = MI.getOperand(0).isDead();
201 bool DstIsKill = MI.getOperand(1).isKill();
202 bool SrcIsKill = MI.getOperand(2).isKill();
203 bool ImpIsDead = MI.getOperand(3).isDead();
204 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
205 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
206
207 auto MIBLO =
208 buildMI(MBB, MBBI, Op)
209 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
210 .addReg(DstLoReg, getKillRegState(DstIsKill))
211 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
212
213 // SREG is always implicitly dead
214 MIBLO->getOperand(3).setIsDead();
215
216 auto MIBHI =
217 buildMI(MBB, MBBI, Op)
218 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
219 .addReg(DstHiReg, getKillRegState(DstIsKill))
220 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
221
222 if (ImpIsDead)
223 MIBHI->getOperand(3).setIsDead();
224
225 MI.eraseFromParent();
226 return true;
227}
228
229bool AVRExpandPseudoImpl::isLogicImmOpRedundant(unsigned Op,
230 unsigned ImmVal) const {
231
232 // ANDI Rd, 0xff is redundant.
233 if (Op == AVR::ANDIRdK && ImmVal == 0xff)
234 return true;
235
236 // ORI Rd, 0x0 is redundant.
237 if (Op == AVR::ORIRdK && ImmVal == 0x0)
238 return true;
239
240 return false;
241}
242
243bool AVRExpandPseudoImpl::isLogicRegOpUndef(unsigned Op,
244 unsigned ImmVal) const {
245 // ANDI Rd, 0x00 clears all input bits.
246 if (Op == AVR::ANDIRdK && ImmVal == 0x00)
247 return true;
248
249 // ORI Rd, 0xff sets all input bits.
250 if (Op == AVR::ORIRdK && ImmVal == 0xff)
251 return true;
252
253 return false;
254}
255
256bool AVRExpandPseudoImpl::expandLogicImm(unsigned Op, Block &MBB,
257 BlockIt MBBI) {
258 MachineInstr &MI = *MBBI;
259 Register DstLoReg, DstHiReg;
260 Register DstReg = MI.getOperand(0).getReg();
261 bool DstIsDead = MI.getOperand(0).isDead();
262 bool SrcIsKill = MI.getOperand(1).isKill();
263 bool ImpIsDead = MI.getOperand(3).isDead();
264 unsigned Imm = MI.getOperand(2).getImm();
265 unsigned Lo8 = Imm & 0xff;
266 unsigned Hi8 = (Imm >> 8) & 0xff;
267 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
268
269 if (!isLogicImmOpRedundant(Op, Lo8)) {
270 auto MIBLO =
271 buildMI(MBB, MBBI, Op)
272 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
273 .addReg(DstLoReg, getKillRegState(SrcIsKill))
274 .addImm(Lo8);
275
276 // SREG is always implicitly dead
277 MIBLO->getOperand(3).setIsDead();
278
279 if (isLogicRegOpUndef(Op, Lo8))
280 MIBLO->getOperand(1).setIsUndef(true);
281 }
282
283 if (!isLogicImmOpRedundant(Op, Hi8)) {
284 auto MIBHI =
285 buildMI(MBB, MBBI, Op)
286 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
287 .addReg(DstHiReg, getKillRegState(SrcIsKill))
288 .addImm(Hi8);
289
290 if (ImpIsDead)
291 MIBHI->getOperand(3).setIsDead();
292
293 if (isLogicRegOpUndef(Op, Hi8))
294 MIBHI->getOperand(1).setIsUndef(true);
295 }
296
297 MI.eraseFromParent();
298 return true;
299}
300
301template <>
302bool AVRExpandPseudoImpl::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
303 return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI);
304}
305
306template <>
307bool AVRExpandPseudoImpl::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI) {
308 return expandArith(AVR::ADCRdRr, AVR::ADCRdRr, MBB, MBBI);
309}
310
311template <>
312bool AVRExpandPseudoImpl::expand<AVR::ADIWRdKP>(Block &MBB, BlockIt MBBI) {
313 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
314 MachineInstr &MI = *MBBI;
315 Register DstReg = MI.getOperand(0).getReg();
316 Register SrcReg = MI.getOperand(1).getReg();
317 int64_t Imm = MI.getOperand(2).getImm();
318 unsigned Opcode;
319
320 if (SrcReg != DstReg) {
321 TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DstReg, SrcReg, false, false,
322 false);
323 }
324
325 if (isUInt<6>(Imm) && STI.hasADDSUBIW() &&
326 AVR::IWREGSRegClass.contains(DstReg)) {
327 Opcode = AVR::ADIWRdK;
328 } else {
329 Opcode = AVR::SUBIWRdK;
330 Imm = -Imm;
331 }
332
333 buildMI(MBB, MI, Opcode)
334 .addReg(DstReg, RegState::Define)
335 .addReg(DstReg, RegState::Kill)
336 .addImm(Imm)
337 .setOperandDead(3); // implicit-def $sreg
338
339 MI.eraseFromParent();
340 return true;
341}
342
343template <>
344bool AVRExpandPseudoImpl::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) {
345 return expandArith(AVR::SUBRdRr, AVR::SBCRdRr, MBB, MBBI);
346}
347
348template <>
349bool AVRExpandPseudoImpl::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {
350 MachineInstr &MI = *MBBI;
351 Register DstLoReg, DstHiReg;
352 Register DstReg = MI.getOperand(0).getReg();
353 bool DstIsDead = MI.getOperand(0).isDead();
354 bool SrcIsKill = MI.getOperand(1).isKill();
355 bool ImpIsDead = MI.getOperand(3).isDead();
356 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
357
358 auto MIBLO =
359 buildMI(MBB, MBBI, AVR::SUBIRdK)
360 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
361 .addReg(DstLoReg, getKillRegState(SrcIsKill));
362
363 auto MIBHI =
364 buildMI(MBB, MBBI, AVR::SBCIRdK)
365 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
366 .addReg(DstHiReg, getKillRegState(SrcIsKill));
367
368 switch (MI.getOperand(2).getType()) {
369 case MachineOperand::MO_GlobalAddress: {
370 const GlobalValue *GV = MI.getOperand(2).getGlobal();
371 int64_t Offs = MI.getOperand(2).getOffset();
372 unsigned TF = MI.getOperand(2).getTargetFlags();
373 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_LO);
374 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_HI);
375 break;
376 }
377 case MachineOperand::MO_Immediate: {
378 unsigned Imm = MI.getOperand(2).getImm();
379 MIBLO.addImm(Imm & 0xff);
380 MIBHI.addImm((Imm >> 8) & 0xff);
381 break;
382 }
383 default:
384 llvm_unreachable("Unknown operand type!");
385 }
386
387 if (ImpIsDead)
388 MIBHI->getOperand(3).setIsDead();
389
390 // SREG is always implicitly killed
391 MIBHI->getOperand(4).setIsKill();
392
393 MI.eraseFromParent();
394 return true;
395}
396
397template <>
398bool AVRExpandPseudoImpl::expand<AVR::SBCWRdRr>(Block &MBB, BlockIt MBBI) {
399 return expandArith(AVR::SBCRdRr, AVR::SBCRdRr, MBB, MBBI);
400}
401
402template <>
403bool AVRExpandPseudoImpl::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {
404 MachineInstr &MI = *MBBI;
405 Register DstLoReg, DstHiReg;
406 Register DstReg = MI.getOperand(0).getReg();
407 bool DstIsDead = MI.getOperand(0).isDead();
408 bool SrcIsKill = MI.getOperand(1).isKill();
409 bool ImpIsDead = MI.getOperand(3).isDead();
410 unsigned Imm = MI.getOperand(2).getImm();
411 unsigned Lo8 = Imm & 0xff;
412 unsigned Hi8 = (Imm >> 8) & 0xff;
413 unsigned OpLo = AVR::SBCIRdK;
414 unsigned OpHi = AVR::SBCIRdK;
415 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
416
417 auto MIBLO =
418 buildMI(MBB, MBBI, OpLo)
419 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
420 .addReg(DstLoReg, getKillRegState(SrcIsKill))
421 .addImm(Lo8);
422
423 // SREG is always implicitly killed
424 MIBLO->getOperand(4).setIsKill();
425
426 auto MIBHI =
427 buildMI(MBB, MBBI, OpHi)
428 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
429 .addReg(DstHiReg, getKillRegState(SrcIsKill))
430 .addImm(Hi8);
431
432 if (ImpIsDead)
433 MIBHI->getOperand(3).setIsDead();
434
435 // SREG is always implicitly killed
436 MIBHI->getOperand(4).setIsKill();
437
438 MI.eraseFromParent();
439 return true;
440}
441
442template <>
443bool AVRExpandPseudoImpl::expand<AVR::ANDWRdRr>(Block &MBB, BlockIt MBBI) {
444 return expandLogic(AVR::ANDRdRr, MBB, MBBI);
445}
446
447template <>
448bool AVRExpandPseudoImpl::expand<AVR::ANDIWRdK>(Block &MBB, BlockIt MBBI) {
449 return expandLogicImm(AVR::ANDIRdK, MBB, MBBI);
450}
451
452template <>
453bool AVRExpandPseudoImpl::expand<AVR::ORWRdRr>(Block &MBB, BlockIt MBBI) {
454 return expandLogic(AVR::ORRdRr, MBB, MBBI);
455}
456
457template <>
458bool AVRExpandPseudoImpl::expand<AVR::ORIWRdK>(Block &MBB, BlockIt MBBI) {
459 return expandLogicImm(AVR::ORIRdK, MBB, MBBI);
460}
461
462template <>
463bool AVRExpandPseudoImpl::expand<AVR::EORWRdRr>(Block &MBB, BlockIt MBBI) {
464 return expandLogic(AVR::EORRdRr, MBB, MBBI);
465}
466
467template <>
468bool AVRExpandPseudoImpl::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {
469 MachineInstr &MI = *MBBI;
470 Register DstLoReg, DstHiReg;
471 Register DstReg = MI.getOperand(0).getReg();
472 bool DstIsDead = MI.getOperand(0).isDead();
473 bool DstIsKill = MI.getOperand(1).isKill();
474 bool ImpIsDead = MI.getOperand(2).isDead();
475 unsigned OpLo = AVR::COMRd;
476 unsigned OpHi = AVR::COMRd;
477 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
478
479 auto MIBLO =
480 buildMI(MBB, MBBI, OpLo)
481 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
482 .addReg(DstLoReg, getKillRegState(DstIsKill));
483
484 // SREG is always implicitly dead
485 MIBLO->getOperand(2).setIsDead();
486
487 auto MIBHI =
488 buildMI(MBB, MBBI, OpHi)
489 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
490 .addReg(DstHiReg, getKillRegState(DstIsKill));
491
492 if (ImpIsDead)
493 MIBHI->getOperand(2).setIsDead();
494
495 MI.eraseFromParent();
496 return true;
497}
498
499template <>
500bool AVRExpandPseudoImpl::expand<AVR::NEGWRd>(Block &MBB, BlockIt MBBI) {
501 MachineInstr &MI = *MBBI;
502 Register DstLoReg, DstHiReg;
503 Register DstReg = MI.getOperand(0).getReg();
504 Register ZeroReg = MI.getOperand(2).getReg();
505 bool DstIsDead = MI.getOperand(0).isDead();
506 bool DstIsKill = MI.getOperand(1).isKill();
507 bool ImpIsDead = MI.getOperand(2).isDead();
508 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
509
510 // Do NEG on the upper byte.
511 auto MIBHI =
512 buildMI(MBB, MBBI, AVR::NEGRd)
513 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
514 .addReg(DstHiReg, RegState::Kill);
515 // SREG is always implicitly dead
516 MIBHI->getOperand(2).setIsDead();
517
518 // Do NEG on the lower byte.
519 buildMI(MBB, MBBI, AVR::NEGRd)
520 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
521 .addReg(DstLoReg, getKillRegState(DstIsKill));
522
523 // Do an extra SBC.
524 auto MISBCI =
525 buildMI(MBB, MBBI, AVR::SBCRdRr)
526 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
527 .addReg(DstHiReg, getKillRegState(DstIsKill))
528 .addReg(ZeroReg);
529 if (ImpIsDead)
530 MISBCI->getOperand(3).setIsDead();
531 // SREG is always implicitly killed
532 MISBCI->getOperand(4).setIsKill();
533
534 MI.eraseFromParent();
535 return true;
536}
537
538template <>
539bool AVRExpandPseudoImpl::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {
540 MachineInstr &MI = *MBBI;
541 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
542 Register DstReg = MI.getOperand(0).getReg();
543 Register SrcReg = MI.getOperand(1).getReg();
544 bool DstIsKill = MI.getOperand(0).isKill();
545 bool SrcIsKill = MI.getOperand(1).isKill();
546 bool ImpIsDead = MI.getOperand(2).isDead();
547 unsigned OpLo = AVR::CPRdRr;
548 unsigned OpHi = AVR::CPCRdRr;
549 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
550 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
551
552 // Low part
553 buildMI(MBB, MBBI, OpLo)
554 .addReg(DstLoReg, getKillRegState(DstIsKill))
555 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
556
557 auto MIBHI = buildMI(MBB, MBBI, OpHi)
558 .addReg(DstHiReg, getKillRegState(DstIsKill))
559 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
560
561 if (ImpIsDead)
562 MIBHI->getOperand(2).setIsDead();
563
564 // SREG is always implicitly killed
565 MIBHI->getOperand(3).setIsKill();
566
567 MI.eraseFromParent();
568 return true;
569}
570
571template <>
572bool AVRExpandPseudoImpl::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {
573 MachineInstr &MI = *MBBI;
574 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
575 Register DstReg = MI.getOperand(0).getReg();
576 Register SrcReg = MI.getOperand(1).getReg();
577 bool DstIsKill = MI.getOperand(0).isKill();
578 bool SrcIsKill = MI.getOperand(1).isKill();
579 bool ImpIsDead = MI.getOperand(2).isDead();
580 unsigned OpLo = AVR::CPCRdRr;
581 unsigned OpHi = AVR::CPCRdRr;
582 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
583 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
584
585 auto MIBLO = buildMI(MBB, MBBI, OpLo)
586 .addReg(DstLoReg, getKillRegState(DstIsKill))
587 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
588
589 // SREG is always implicitly killed
590 MIBLO->getOperand(3).setIsKill();
591
592 auto MIBHI = buildMI(MBB, MBBI, OpHi)
593 .addReg(DstHiReg, getKillRegState(DstIsKill))
594 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
595
596 if (ImpIsDead)
597 MIBHI->getOperand(2).setIsDead();
598
599 // SREG is always implicitly killed
600 MIBHI->getOperand(3).setIsKill();
601
602 MI.eraseFromParent();
603 return true;
604}
605
606template <>
607bool AVRExpandPseudoImpl::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {
608 MachineInstr &MI = *MBBI;
609 Register DstLoReg, DstHiReg;
610 Register DstReg = MI.getOperand(0).getReg();
611 bool DstIsDead = MI.getOperand(0).isDead();
612 unsigned OpLo = AVR::LDIRdK;
613 unsigned OpHi = AVR::LDIRdK;
614 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
615
616 auto MIBLO =
617 buildMI(MBB, MBBI, OpLo)
618 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
619
620 auto MIBHI =
621 buildMI(MBB, MBBI, OpHi)
622 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
623
624 switch (MI.getOperand(1).getType()) {
625 case MachineOperand::MO_GlobalAddress: {
626 const GlobalValue *GV = MI.getOperand(1).getGlobal();
627 int64_t Offs = MI.getOperand(1).getOffset();
628 unsigned TF = MI.getOperand(1).getTargetFlags();
629
630 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_LO);
631 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_HI);
632 break;
633 }
634 case MachineOperand::MO_BlockAddress: {
635 const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
636 unsigned TF = MI.getOperand(1).getTargetFlags();
637
638 MIBLO.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_LO));
639 MIBHI.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_HI));
640 break;
641 }
642 case MachineOperand::MO_Immediate: {
643 unsigned Imm = MI.getOperand(1).getImm();
644
645 MIBLO.addImm(Imm & 0xff);
646 MIBHI.addImm((Imm >> 8) & 0xff);
647 break;
648 }
649 default:
650 llvm_unreachable("Unknown operand type!");
651 }
652
653 MI.eraseFromParent();
654 return true;
655}
656
657template <>
658bool AVRExpandPseudoImpl::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
659 MachineInstr &MI = *MBBI;
660 Register DstLoReg, DstHiReg;
661 Register DstReg = MI.getOperand(0).getReg();
662 bool DstIsDead = MI.getOperand(0).isDead();
663 unsigned OpLo = AVR::LDSRdK;
664 unsigned OpHi = AVR::LDSRdK;
665 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
666
667 auto MIBLO =
668 buildMI(MBB, MBBI, OpLo)
669 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
670
671 auto MIBHI =
672 buildMI(MBB, MBBI, OpHi)
673 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
674
675 switch (MI.getOperand(1).getType()) {
676 case MachineOperand::MO_GlobalAddress: {
677 const GlobalValue *GV = MI.getOperand(1).getGlobal();
678 int64_t Offs = MI.getOperand(1).getOffset();
679 unsigned TF = MI.getOperand(1).getTargetFlags();
680
681 MIBLO.addGlobalAddress(GV, Offs, TF);
682 MIBHI.addGlobalAddress(GV, Offs + 1, TF);
683 break;
684 }
685 case MachineOperand::MO_Immediate: {
686 unsigned Imm = MI.getOperand(1).getImm();
687
688 MIBLO.addImm(Imm);
689 MIBHI.addImm(Imm + 1);
690 break;
691 }
692 default:
693 llvm_unreachable("Unknown operand type!");
694 }
695
696 MIBLO.setMemRefs(MI.memoperands());
697 MIBHI.setMemRefs(MI.memoperands());
698
699 MI.eraseFromParent();
700 return true;
701}
702
703template <>
704bool AVRExpandPseudoImpl::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
705 MachineInstr &MI = *MBBI;
706 Register DstReg = MI.getOperand(0).getReg();
707 Register SrcReg = MI.getOperand(1).getReg();
708 bool DstIsKill = MI.getOperand(0).isKill();
709 bool SrcIsKill = MI.getOperand(1).isKill();
710 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
711
712 // DstReg has an earlyclobber so the register allocator will allocate them in
713 // separate registers.
714 assert(DstReg != SrcReg && "Dst and Src registers are the same!");
715
716 if (STI.hasTinyEncoding()) {
717 // Handle this case in the expansion of LDDWRdPtrQ because it is very
718 // similar.
719 buildMI(MBB, MBBI, AVR::LDDWRdPtrQ)
720 .addDef(DstReg, getKillRegState(DstIsKill))
721 .addReg(SrcReg, getKillRegState(SrcIsKill))
722 .addImm(0)
723 .setMemRefs(MI.memoperands());
724
725 } else {
726 Register DstLoReg, DstHiReg;
727 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
728
729 // Load low byte.
730 buildMI(MBB, MBBI, AVR::LDRdPtr)
731 .addReg(DstLoReg, RegState::Define)
732 .addReg(SrcReg)
733 .setMemRefs(MI.memoperands());
734
735 // Load high byte.
736 buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
737 .addReg(DstHiReg, RegState::Define)
738 .addReg(SrcReg, getKillRegState(SrcIsKill))
739 .addImm(1)
740 .setMemRefs(MI.memoperands());
741 }
742
743 MI.eraseFromParent();
744 return true;
745}
746
747template <>
748bool AVRExpandPseudoImpl::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
749 MachineInstr &MI = *MBBI;
750 Register DstLoReg, DstHiReg;
751 Register DstReg = MI.getOperand(0).getReg();
752 Register SrcReg = MI.getOperand(1).getReg();
753 bool DstIsDead = MI.getOperand(0).isDead();
754 bool SrcIsDead = MI.getOperand(1).isKill();
755 unsigned OpLo = AVR::LDRdPtrPi;
756 unsigned OpHi = AVR::LDRdPtrPi;
757 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
758
759 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
760
761 auto MIBLO =
762 buildMI(MBB, MBBI, OpLo)
763 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
764 .addReg(SrcReg, RegState::Define)
765 .addReg(SrcReg, RegState::Kill);
766
767 auto MIBHI =
768 buildMI(MBB, MBBI, OpHi)
769 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
770 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
771 .addReg(SrcReg, RegState::Kill);
772
773 MIBLO.setMemRefs(MI.memoperands());
774 MIBHI.setMemRefs(MI.memoperands());
775
776 MI.eraseFromParent();
777 return true;
778}
779
780template <>
781bool AVRExpandPseudoImpl::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
782 MachineInstr &MI = *MBBI;
783 Register DstLoReg, DstHiReg;
784 Register DstReg = MI.getOperand(0).getReg();
785 Register SrcReg = MI.getOperand(1).getReg();
786 bool DstIsDead = MI.getOperand(0).isDead();
787 bool SrcIsDead = MI.getOperand(1).isKill();
788 unsigned OpLo = AVR::LDRdPtrPd;
789 unsigned OpHi = AVR::LDRdPtrPd;
790 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
791
792 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
793
794 auto MIBHI =
795 buildMI(MBB, MBBI, OpHi)
796 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
797 .addReg(SrcReg, RegState::Define)
798 .addReg(SrcReg, RegState::Kill);
799
800 auto MIBLO =
801 buildMI(MBB, MBBI, OpLo)
802 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
803 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
804 .addReg(SrcReg, RegState::Kill);
805
806 MIBLO.setMemRefs(MI.memoperands());
807 MIBHI.setMemRefs(MI.memoperands());
808
809 MI.eraseFromParent();
810 return true;
811}
812
813template <>
814bool AVRExpandPseudoImpl::expand<AVR::LDDRdPtrQ>(Block &MBB, BlockIt MBBI) {
815 MachineInstr &MI = *MBBI;
816 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
817
818 // LDDRdPtrQ is a real instruction on ordinary AVR devices, but we treat it
819 // as a pseudo instruction on AVR tiny devices.
820 if (!STI.hasTinyEncoding())
821 return false;
822
823 Register DstReg = MI.getOperand(0).getReg();
824 bool DstIsDead = MI.getOperand(0).isDead();
825 Register SrcReg = MI.getOperand(1).getReg();
826 bool SrcIsKill = MI.getOperand(1).isKill();
827 unsigned Imm = MI.getOperand(2).getImm();
828
829 assert((Imm == 0 || SrcIsKill || !TRI->regsOverlap(DstReg, SrcReg)) &&
830 "Cannot restore a pointer that the load overwrites");
831
832 if (Imm != 0)
833 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg)
834 .addReg(SrcReg, RegState::Kill)
835 .addImm(0x10000 - Imm);
836
837 buildMI(MBB, MBBI, AVR::LDRdPtr)
838 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
839 .addReg(SrcReg, getKillRegState(SrcIsKill))
840 .setMemRefs(MI.memoperands());
841
842 if (Imm != 0 && !SrcIsKill)
843 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg)
844 .addReg(SrcReg, RegState::Kill)
845 .addImm(Imm);
846
847 MI.eraseFromParent();
848 return true;
849}
850
851template <>
852bool AVRExpandPseudoImpl::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
853 MachineInstr &MI = *MBBI;
854 Register DstReg = MI.getOperand(0).getReg();
855 Register SrcReg = MI.getOperand(1).getReg();
856 unsigned Imm = MI.getOperand(2).getImm();
857 bool DstIsKill = MI.getOperand(0).isKill();
858 bool SrcIsKill = MI.getOperand(1).isKill();
859 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
860
861 // Since we add 1 to the Imm value for the high byte below, and 63 is the
862 // highest Imm value allowed for the instruction, 62 is the limit here.
863 assert(Imm <= 62 && "Offset is out of range");
864
865 // DstReg has an earlyclobber so the register allocator will allocate them in
866 // separate registers.
867 assert(DstReg != SrcReg && "Dst and Src registers are the same!");
868
869 if (STI.hasTinyEncoding()) {
870 // Reduced tiny cores don't support load/store with displacement. However,
871 // they do support postincrement. So we'll simply adjust the pointer before
872 // and after and use postincrement to load multiple registers.
873
874 // Add offset. The offset can be 0 when expanding this instruction from the
875 // more specific LDWRdPtr instruction.
876 if (Imm != 0) {
877 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg)
878 .addReg(SrcReg)
879 .addImm(0x10000 - Imm);
880 }
881
882 // Do a word load with postincrement. This will be lowered to a two byte
883 // load.
884 buildMI(MBB, MBBI, AVR::LDWRdPtrPi)
885 .addDef(DstReg, getKillRegState(DstIsKill))
886 .addReg(SrcReg, getKillRegState(SrcIsKill))
887 .addImm(0)
888 .setMemRefs(MI.memoperands());
889
890 // If the pointer is used after the store instruction, subtract the new
891 // offset (with 2 added after the postincrement instructions) so it is the
892 // same as before.
893 if (!SrcIsKill) {
894 buildMI(MBB, MBBI, AVR::SUBIWRdK, SrcReg).addReg(SrcReg).addImm(Imm + 2);
895 }
896 } else {
897 Register DstLoReg, DstHiReg;
898 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
899
900 // Load low byte.
901 buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
902 .addReg(DstLoReg, RegState::Define)
903 .addReg(SrcReg)
904 .addImm(Imm)
905 .setMemRefs(MI.memoperands());
906
907 // Load high byte.
908 buildMI(MBB, MBBI, AVR::LDDRdPtrQ)
909 .addReg(DstHiReg, RegState::Define)
910 .addReg(SrcReg, getKillRegState(SrcIsKill))
911 .addImm(Imm + 1)
912 .setMemRefs(MI.memoperands());
913 }
914
915 MI.eraseFromParent();
916 return true;
917}
918
919bool AVRExpandPseudoImpl::expandLPMWELPMW(Block &MBB, BlockIt MBBI,
920 bool IsELPM) {
921 MachineInstr &MI = *MBBI;
922 Register DstLoReg, DstHiReg;
923 Register DstReg = MI.getOperand(0).getReg();
924 Register SrcReg = MI.getOperand(1).getReg();
925 Register SrcLoReg, SrcHiReg;
926 bool SrcIsKill = MI.getOperand(1).isKill();
927 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
928 bool IsLPMRn = IsELPM ? STI.hasELPMX() : STI.hasLPMX();
929
930 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
931 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
932
933 // Set the I/O register RAMPZ for ELPM.
934 if (IsELPM) {
935 Register Bank = MI.getOperand(2).getReg();
936 // out RAMPZ, rtmp
937 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(Bank);
938 }
939
940 // This is enforced by the @earlyclobber constraint.
941 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
942
943 if (IsLPMRn) {
944 unsigned OpLo = IsELPM ? AVR::ELPMRdZPi : AVR::LPMRdZPi;
945 unsigned OpHi = IsELPM ? AVR::ELPMRdZ : AVR::LPMRdZ;
946 // Load low byte.
947 auto MIBLO = buildMI(MBB, MBBI, OpLo)
948 .addReg(DstLoReg, RegState::Define)
949 .addReg(SrcReg);
950 // Load high byte.
951 auto MIBHI = buildMI(MBB, MBBI, OpHi)
952 .addReg(DstHiReg, RegState::Define)
953 .addReg(SrcReg, getKillRegState(SrcIsKill));
954 MIBLO.setMemRefs(MI.memoperands());
955 MIBHI.setMemRefs(MI.memoperands());
956 } else {
957 unsigned Opc = IsELPM ? AVR::ELPM : AVR::LPM;
958 // Load low byte, and copy to the low destination register.
959 auto MIBLO = buildMI(MBB, MBBI, Opc);
960 buildMI(MBB, MBBI, AVR::MOVRdRr)
961 .addReg(DstLoReg, RegState::Define)
962 .addReg(STI.getTmpRegister(), RegState::Kill);
963 MIBLO.setMemRefs(MI.memoperands());
964 // Increase the Z register by 1.
965 if (STI.hasADDSUBIW()) {
966 // adiw r31:r30, 1
967 auto MIINC = buildMI(MBB, MBBI, AVR::ADIWRdK)
968 .addReg(SrcReg, RegState::Define)
969 .addReg(SrcReg, getKillRegState(SrcIsKill))
970 .addImm(1);
971 MIINC->getOperand(3).setIsDead();
972 } else {
973 // subi r30, 255
974 // sbci r31, 255
975 buildMI(MBB, MBBI, AVR::SUBIRdK)
976 .addReg(SrcLoReg, RegState::Define)
977 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
978 .addImm(255);
979 auto MIZHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
980 .addReg(SrcHiReg, RegState::Define)
981 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
982 .addImm(255);
983 MIZHI->getOperand(3).setIsDead();
984 MIZHI->getOperand(4).setIsKill();
985 }
986 // Load high byte, and copy to the high destination register.
987 auto MIBHI = buildMI(MBB, MBBI, Opc);
988 buildMI(MBB, MBBI, AVR::MOVRdRr)
989 .addReg(DstHiReg, RegState::Define)
990 .addReg(STI.getTmpRegister(), RegState::Kill);
991 MIBHI.setMemRefs(MI.memoperands());
992 }
993
994 // Restore the Z register if it is not killed.
995 if (!SrcIsKill) {
996 if (STI.hasADDSUBIW()) {
997 // sbiw r31:r30, 1
998 auto MIDEC = buildMI(MBB, MBBI, AVR::SBIWRdK)
999 .addReg(SrcReg, RegState::Define)
1000 .addReg(SrcReg, getKillRegState(SrcIsKill))
1001 .addImm(1);
1002 MIDEC->getOperand(3).setIsDead();
1003 } else {
1004 // subi r30, 1
1005 // sbci r31, 0
1006 buildMI(MBB, MBBI, AVR::SUBIRdK)
1007 .addReg(SrcLoReg, RegState::Define)
1008 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1009 .addImm(1);
1010 auto MIZHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
1011 .addReg(SrcHiReg, RegState::Define)
1012 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1013 .addImm(0);
1014 MIZHI->getOperand(3).setIsDead();
1015 MIZHI->getOperand(4).setIsKill();
1016 }
1017 }
1018
1019 MI.eraseFromParent();
1020 return true;
1021}
1022
1023template <>
1024bool AVRExpandPseudoImpl::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
1025 return expandLPMWELPMW(MBB, MBBI, false);
1026}
1027
1028template <>
1029bool AVRExpandPseudoImpl::expand<AVR::ELPMWRdZ>(Block &MBB, BlockIt MBBI) {
1030 return expandLPMWELPMW(MBB, MBBI, true);
1031}
1032
1033bool AVRExpandPseudoImpl::expandLPMBELPMB(Block &MBB, BlockIt MBBI,
1034 bool IsELPM) {
1035 MachineInstr &MI = *MBBI;
1036 Register DstReg = MI.getOperand(0).getReg();
1037 Register SrcReg = MI.getOperand(1).getReg();
1038 bool SrcIsKill = MI.getOperand(1).isKill();
1039 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1040 bool IsLPMRn = IsELPM ? STI.hasELPMX() : STI.hasLPMX();
1041
1042 // Set the I/O register RAMPZ for ELPM (out RAMPZ, rtmp).
1043 if (IsELPM) {
1044 Register BankReg = MI.getOperand(2).getReg();
1045 buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(BankReg);
1046 }
1047
1048 // Load byte.
1049 if (IsLPMRn) {
1050 unsigned Opc = IsELPM ? AVR::ELPMRdZ : AVR::LPMRdZ;
1051 auto MILB = buildMI(MBB, MBBI, Opc)
1052 .addReg(DstReg, RegState::Define)
1053 .addReg(SrcReg, getKillRegState(SrcIsKill));
1054 MILB.setMemRefs(MI.memoperands());
1055 } else {
1056 // For the basic ELPM/LPM instruction, its operand[0] is the implicit
1057 // 'Z' register, and its operand[1] is the implicit 'R0' register.
1058 unsigned Opc = IsELPM ? AVR::ELPM : AVR::LPM;
1059 auto MILB = buildMI(MBB, MBBI, Opc);
1060 buildMI(MBB, MBBI, AVR::MOVRdRr)
1061 .addReg(DstReg, RegState::Define)
1062 .addReg(STI.getTmpRegister(), RegState::Kill);
1063 MILB.setMemRefs(MI.memoperands());
1064 }
1065
1066 MI.eraseFromParent();
1067 return true;
1068}
1069
1070template <>
1071bool AVRExpandPseudoImpl::expand<AVR::ELPMBRdZ>(Block &MBB, BlockIt MBBI) {
1072 return expandLPMBELPMB(MBB, MBBI, true);
1073}
1074
1075template <>
1076bool AVRExpandPseudoImpl::expand<AVR::LPMBRdZ>(Block &MBB, BlockIt MBBI) {
1077 return expandLPMBELPMB(MBB, MBBI, false);
1078}
1079
1080template <>
1081bool AVRExpandPseudoImpl::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
1082 llvm_unreachable("16-bit LPMPi is unimplemented");
1083}
1084
1085template <>
1086bool AVRExpandPseudoImpl::expand<AVR::ELPMBRdZPi>(Block &MBB, BlockIt MBBI) {
1087 llvm_unreachable("8-bit ELPMPi is unimplemented");
1088}
1089
1090template <>
1091bool AVRExpandPseudoImpl::expand<AVR::ELPMWRdZPi>(Block &MBB, BlockIt MBBI) {
1092 llvm_unreachable("16-bit ELPMPi is unimplemented");
1093}
1094
1095template <typename Func>
1096bool AVRExpandPseudoImpl::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
1097 MachineInstr &MI = *MBBI;
1098 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1099
1100 // Store the SREG.
1101 buildMI(MBB, MBBI, AVR::INRdA)
1102 .addReg(STI.getTmpRegister(), RegState::Define)
1103 .addImm(STI.getIORegSREG());
1104
1105 // Disable exceptions.
1106 buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
1107
1108 f(MI);
1109
1110 // Restore the status reg.
1111 buildMI(MBB, MBBI, AVR::OUTARr)
1112 .addImm(STI.getIORegSREG())
1113 .addReg(STI.getTmpRegister());
1114
1115 MI.eraseFromParent();
1116 return true;
1117}
1118
1119template <typename Func>
1120bool AVRExpandPseudoImpl::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
1121 BlockIt MBBI, Func f) {
1122 return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
1123 auto Op1 = MI.getOperand(0);
1124 auto Op2 = MI.getOperand(1);
1125
1126 MachineInstr &NewInst =
1127 *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
1128 f(NewInst);
1129 });
1130}
1131
1132bool AVRExpandPseudoImpl::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
1133 BlockIt MBBI) {
1134 return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {});
1135}
1136
1137template <>
1138bool AVRExpandPseudoImpl::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
1139 return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
1140}
1141
1142template <>
1143bool AVRExpandPseudoImpl::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
1144 return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
1145}
1146
1147template <>
1148bool AVRExpandPseudoImpl::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
1149 return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
1150}
1151
1152template <>
1153bool AVRExpandPseudoImpl::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
1154 return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
1155}
1156
1157template <>
1158bool AVRExpandPseudoImpl::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
1159 // On AVR, there is only one core and so atomic fences do nothing.
1160 MBBI->eraseFromParent();
1161 return true;
1162}
1163
1164template <>
1165bool AVRExpandPseudoImpl::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
1166 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1167 MachineInstr &MI = *MBBI;
1168 Register SrcLoReg, SrcHiReg;
1169 Register SrcReg = MI.getOperand(1).getReg();
1170 bool SrcIsKill = MI.getOperand(1).isKill();
1171 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1172
1173 auto MIB0 = buildMI(MBB, MBBI, AVR::STSKRr);
1174 auto MIB1 = buildMI(MBB, MBBI, AVR::STSKRr);
1175
1176 switch (MI.getOperand(0).getType()) {
1177 case MachineOperand::MO_GlobalAddress: {
1178 const GlobalValue *GV = MI.getOperand(0).getGlobal();
1179 int64_t Offs = MI.getOperand(0).getOffset();
1180 unsigned TF = MI.getOperand(0).getTargetFlags();
1181
1182 if (STI.hasLowByteFirst()) {
1183 // Write the low byte first for XMEGA devices.
1184 MIB0.addGlobalAddress(GV, Offs, TF);
1185 MIB1.addGlobalAddress(GV, Offs + 1, TF);
1186 } else {
1187 // Write the high byte first for traditional devices.
1188 MIB0.addGlobalAddress(GV, Offs + 1, TF);
1189 MIB1.addGlobalAddress(GV, Offs, TF);
1190 }
1191
1192 break;
1193 }
1194 case MachineOperand::MO_Immediate: {
1195 unsigned Imm = MI.getOperand(0).getImm();
1196
1197 if (STI.hasLowByteFirst()) {
1198 // Write the low byte first for XMEGA devices.
1199 MIB0.addImm(Imm);
1200 MIB1.addImm(Imm + 1);
1201 } else {
1202 // Write the high byte first for traditional devices.
1203 MIB0.addImm(Imm + 1);
1204 MIB1.addImm(Imm);
1205 }
1206
1207 break;
1208 }
1209 default:
1210 llvm_unreachable("Unknown operand type!");
1211 }
1212
1213 if (STI.hasLowByteFirst()) {
1214 // Write the low byte first for XMEGA devices.
1215 MIB0.addReg(SrcLoReg, getKillRegState(SrcIsKill))
1216 .setMemRefs(MI.memoperands());
1217 MIB1.addReg(SrcHiReg, getKillRegState(SrcIsKill))
1218 .setMemRefs(MI.memoperands());
1219 } else {
1220 // Write the high byte first for traditional devices.
1221 MIB0.addReg(SrcHiReg, getKillRegState(SrcIsKill))
1222 .setMemRefs(MI.memoperands());
1223 MIB1.addReg(SrcLoReg, getKillRegState(SrcIsKill))
1224 .setMemRefs(MI.memoperands());
1225 }
1226
1227 MI.eraseFromParent();
1228 return true;
1229}
1230
1231template <>
1232bool AVRExpandPseudoImpl::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
1233 MachineInstr &MI = *MBBI;
1234 Register DstReg = MI.getOperand(0).getReg();
1235 Register SrcReg = MI.getOperand(1).getReg();
1236 bool DstIsKill = MI.getOperand(0).isKill();
1237 bool DstIsUndef = MI.getOperand(0).isUndef();
1238 bool SrcIsKill = MI.getOperand(1).isKill();
1239 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1240
1241 if (STI.hasTinyEncoding()) {
1242 // Handle this case in the expansion of STDWPtrQRr because it is very
1243 // similar.
1244 buildMI(MBB, MBBI, AVR::STDWPtrQRr)
1245 .addReg(DstReg,
1246 getKillRegState(DstIsKill) | getUndefRegState(DstIsUndef))
1247 .addImm(0)
1248 .addReg(SrcReg, getKillRegState(SrcIsKill))
1249 .setMemRefs(MI.memoperands());
1250
1251 } else {
1252 Register SrcLoReg, SrcHiReg;
1253 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1254 if (STI.hasLowByteFirst()) {
1255 buildMI(MBB, MBBI, AVR::STPtrRr)
1256 .addReg(DstReg, getUndefRegState(DstIsUndef))
1257 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1258 .setMemRefs(MI.memoperands());
1259 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1260 .addReg(DstReg, getUndefRegState(DstIsUndef))
1261 .addImm(1)
1262 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1263 .setMemRefs(MI.memoperands());
1264 } else {
1265 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1266 .addReg(DstReg, getUndefRegState(DstIsUndef))
1267 .addImm(1)
1268 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1269 .setMemRefs(MI.memoperands());
1270 buildMI(MBB, MBBI, AVR::STPtrRr)
1271 .addReg(DstReg, getUndefRegState(DstIsUndef))
1272 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1273 .setMemRefs(MI.memoperands());
1274 }
1275 }
1276
1277 MI.eraseFromParent();
1278 return true;
1279}
1280
1281template <>
1282bool AVRExpandPseudoImpl::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
1283 MachineInstr &MI = *MBBI;
1284 Register SrcLoReg, SrcHiReg;
1285 Register DstReg = MI.getOperand(0).getReg();
1286 Register SrcReg = MI.getOperand(2).getReg();
1287 unsigned Imm = MI.getOperand(3).getImm();
1288 bool DstIsDead = MI.getOperand(0).isDead();
1289 bool SrcIsKill = MI.getOperand(2).isKill();
1290 unsigned OpLo = AVR::STPtrPiRr;
1291 unsigned OpHi = AVR::STPtrPiRr;
1292 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1293
1294 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1295
1296 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1297 .addReg(DstReg, RegState::Define)
1298 .addReg(DstReg, RegState::Kill)
1299 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1300 .addImm(Imm);
1301
1302 auto MIBHI =
1303 buildMI(MBB, MBBI, OpHi)
1304 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1305 .addReg(DstReg, RegState::Kill)
1306 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1307 .addImm(Imm);
1308
1309 MIBLO.setMemRefs(MI.memoperands());
1310 MIBHI.setMemRefs(MI.memoperands());
1311
1312 MI.eraseFromParent();
1313 return true;
1314}
1315
1316template <>
1317bool AVRExpandPseudoImpl::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
1318 MachineInstr &MI = *MBBI;
1319 Register SrcLoReg, SrcHiReg;
1320 Register DstReg = MI.getOperand(0).getReg();
1321 Register SrcReg = MI.getOperand(2).getReg();
1322 unsigned Imm = MI.getOperand(3).getImm();
1323 bool DstIsDead = MI.getOperand(0).isDead();
1324 bool SrcIsKill = MI.getOperand(2).isKill();
1325 unsigned OpLo = AVR::STPtrPdRr;
1326 unsigned OpHi = AVR::STPtrPdRr;
1327 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1328
1329 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1330
1331 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1332 .addReg(DstReg, RegState::Define)
1333 .addReg(DstReg, RegState::Kill)
1334 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1335 .addImm(Imm);
1336
1337 auto MIBLO =
1338 buildMI(MBB, MBBI, OpLo)
1339 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1340 .addReg(DstReg, RegState::Kill)
1341 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1342 .addImm(Imm);
1343
1344 MIBLO.setMemRefs(MI.memoperands());
1345 MIBHI.setMemRefs(MI.memoperands());
1346
1347 MI.eraseFromParent();
1348 return true;
1349}
1350
1351template <>
1352bool AVRExpandPseudoImpl::expand<AVR::STDPtrQRr>(Block &MBB, BlockIt MBBI) {
1353 MachineInstr &MI = *MBBI;
1354 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1355
1356 // STDPtrQRr is a real instruction on ordinary AVR devices, but we treat it
1357 // as a pseudo instruction on AVR tiny devices.
1358 if (!STI.hasTinyEncoding())
1359 return false;
1360
1361 Register DstReg = MI.getOperand(0).getReg();
1362 bool DstIsKill = MI.getOperand(0).isKill();
1363 unsigned Imm = MI.getOperand(1).getImm();
1364 Register SrcReg = MI.getOperand(2).getReg();
1365 bool SrcIsKill = MI.getOperand(2).isKill();
1366
1367 assert((Imm == 0 || !TRI->regsOverlap(DstReg, SrcReg)) &&
1368 "Cannot adjust a pointer that holds the value to store");
1369
1370 if (Imm != 0)
1371 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1372 .addReg(DstReg, RegState::Kill)
1373 .addImm(0x10000 - Imm);
1374
1375 buildMI(MBB, MBBI, AVR::STPtrRr)
1376 .addReg(DstReg, getKillRegState(DstIsKill))
1377 .addReg(SrcReg, getKillRegState(SrcIsKill))
1378 .setMemRefs(MI.memoperands());
1379
1380 if (Imm != 0 && !DstIsKill)
1381 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1382 .addReg(DstReg, RegState::Kill)
1383 .addImm(Imm);
1384
1385 MI.eraseFromParent();
1386 return true;
1387}
1388
1389template <>
1390bool AVRExpandPseudoImpl::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
1391 MachineInstr &MI = *MBBI;
1392 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1393
1394 Register DstReg = MI.getOperand(0).getReg();
1395 bool DstIsKill = MI.getOperand(0).isKill();
1396 unsigned Imm = MI.getOperand(1).getImm();
1397 Register SrcReg = MI.getOperand(2).getReg();
1398 bool SrcIsKill = MI.getOperand(2).isKill();
1399
1400 // STD's maximum displacement is 63, so larger stores have to be split into a
1401 // set of operations.
1402 // For avrtiny chips, STD is not available at all so we always have to fall
1403 // back to manual pointer adjustments.
1404 if (Imm >= 63 || STI.hasTinyEncoding()) {
1405 // Add offset. The offset can be 0 when expanding this instruction from the
1406 // more specific STWPtrRr instruction.
1407 if (Imm != 0) {
1408 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1409 .addReg(DstReg, RegState::Kill)
1410 .addImm(0x10000 - Imm);
1411 }
1412
1413 // Do the store. This is a word store, that will be expanded further.
1414 buildMI(MBB, MBBI, AVR::STWPtrPiRr, DstReg)
1415 .addReg(DstReg, getKillRegState(DstIsKill))
1416 .addReg(SrcReg, getKillRegState(SrcIsKill))
1417 .addImm(0)
1418 .setMemRefs(MI.memoperands());
1419
1420 // If the pointer is used after the store instruction, subtract the new
1421 // offset (with 2 added after the postincrement instructions) so it is the
1422 // same as before.
1423 if (!DstIsKill) {
1424 buildMI(MBB, MBBI, AVR::SUBIWRdK, DstReg)
1425 .addReg(DstReg, RegState::Kill)
1426 .addImm(Imm + 2);
1427 }
1428 } else {
1429 Register SrcLoReg, SrcHiReg;
1430 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1431
1432 if (STI.hasLowByteFirst()) {
1433 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1434 .addReg(DstReg)
1435 .addImm(Imm)
1436 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1437 .setMemRefs(MI.memoperands());
1438 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1439 .addReg(DstReg, getKillRegState(DstIsKill))
1440 .addImm(Imm + 1)
1441 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1442 .setMemRefs(MI.memoperands());
1443 } else {
1444 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1445 .addReg(DstReg)
1446 .addImm(Imm + 1)
1447 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1448 .setMemRefs(MI.memoperands());
1449 buildMI(MBB, MBBI, AVR::STDPtrQRr)
1450 .addReg(DstReg, getKillRegState(DstIsKill))
1451 .addImm(Imm)
1452 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1453 .setMemRefs(MI.memoperands());
1454 }
1455 }
1456
1457 MI.eraseFromParent();
1458 return true;
1459}
1460
1461template <>
1462bool AVRExpandPseudoImpl::expand<AVR::STDSPQRr>(Block &MBB, BlockIt MBBI) {
1463 MachineInstr &MI = *MBBI;
1464 const MachineFunction &MF = *MBB.getParent();
1465 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
1466
1467 assert(MI.getOperand(0).getReg() == AVR::SP &&
1468 "SP is expected as base pointer");
1469
1470 assert(STI.getFrameLowering()->hasReservedCallFrame(MF) &&
1471 "unexpected STDSPQRr pseudo instruction");
1472
1473 if (STI.hasTinyEncoding()) {
1474 // Reduced tiny cores don't support std, so emulate it with a plain store
1475 // and pointer adjustments.
1476 unsigned Imm = MI.getOperand(1).getImm();
1477 Register SrcReg = MI.getOperand(2).getReg();
1478 bool SrcIsKill = MI.getOperand(2).isKill();
1479
1480 if (Imm != 0)
1481 buildMI(MBB, MBBI, AVR::SUBIWRdK, AVR::R29R28)
1482 .addReg(AVR::R29R28, RegState::Kill)
1483 .addImm(0x10000 - Imm);
1484
1485 buildMI(MBB, MBBI, AVR::STPtrRr)
1486 .addReg(AVR::R29R28, RegState::Kill)
1487 .addReg(SrcReg, getKillRegState(SrcIsKill))
1488 .setMemRefs(MI.memoperands());
1489
1490 if (Imm != 0)
1491 buildMI(MBB, std::next(MBBI), AVR::SUBIWRdK, AVR::R29R28)
1492 .addReg(AVR::R29R28, RegState::Kill)
1493 .addImm(Imm);
1494
1495 MI.eraseFromParent();
1496 } else {
1497 MI.setDesc(TII->get(AVR::STDPtrQRr));
1498 MI.getOperand(0).setReg(AVR::R29R28);
1499 }
1500
1501 return true;
1502}
1503
1504template <>
1505bool AVRExpandPseudoImpl::expand<AVR::STDWSPQRr>(Block &MBB, BlockIt MBBI) {
1506 MachineInstr &MI = *MBBI;
1507 const MachineFunction &MF = *MBB.getParent();
1508 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
1509
1510 assert(MI.getOperand(0).getReg() == AVR::SP &&
1511 "SP is expected as base pointer");
1512
1513 assert(STI.getFrameLowering()->hasReservedCallFrame(MF) &&
1514 "unexpected STDWSPQRr pseudo instruction");
1515 (void)STI;
1516
1517 MI.setDesc(TII->get(AVR::STDWPtrQRr));
1518 MI.getOperand(0).setReg(AVR::R29R28);
1519
1520 return true;
1521}
1522
1523template <>
1524bool AVRExpandPseudoImpl::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
1525 MachineInstr &MI = *MBBI;
1526 Register DstLoReg, DstHiReg;
1527 unsigned Imm = MI.getOperand(1).getImm();
1528 Register DstReg = MI.getOperand(0).getReg();
1529 bool DstIsDead = MI.getOperand(0).isDead();
1530 unsigned OpLo = AVR::INRdA;
1531 unsigned OpHi = AVR::INRdA;
1532 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1533
1534 // Since we add 1 to the Imm value for the high byte below, and 63 is the
1535 // highest Imm value allowed for the instruction, 62 is the limit here.
1536 assert(Imm <= 62 && "Address is out of range");
1537
1538 auto MIBLO =
1539 buildMI(MBB, MBBI, OpLo)
1540 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1541 .addImm(Imm);
1542
1543 auto MIBHI =
1544 buildMI(MBB, MBBI, OpHi)
1545 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1546 .addImm(Imm + 1);
1547
1548 MIBLO.setMemRefs(MI.memoperands());
1549 MIBHI.setMemRefs(MI.memoperands());
1550
1551 MI.eraseFromParent();
1552 return true;
1553}
1554
1555template <>
1556bool AVRExpandPseudoImpl::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
1557 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
1558 MachineInstr &MI = *MBBI;
1559 Register SrcLoReg, SrcHiReg;
1560 unsigned Imm = MI.getOperand(0).getImm();
1561 Register SrcReg = MI.getOperand(1).getReg();
1562 bool SrcIsKill = MI.getOperand(1).isKill();
1563 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1564
1565 // Since we add 1 to the Imm value for the high byte below, and 63 is the
1566 // highest Imm value allowed for the instruction, 62 is the limit here.
1567 assert(Imm <= 62 && "Address is out of range");
1568
1569 // 16 bit I/O writes need the high byte first on normal AVR devices,
1570 // and in reverse order for the XMEGA/XMEGA3/XMEGAU families.
1571 auto MIBHI = buildMI(MBB, MBBI, AVR::OUTARr)
1572 .addImm(STI.hasLowByteFirst() ? Imm : Imm + 1)
1573 .addReg(STI.hasLowByteFirst() ? SrcLoReg : SrcHiReg,
1574 getKillRegState(SrcIsKill));
1575 auto MIBLO = buildMI(MBB, MBBI, AVR::OUTARr)
1576 .addImm(STI.hasLowByteFirst() ? Imm + 1 : Imm)
1577 .addReg(STI.hasLowByteFirst() ? SrcHiReg : SrcLoReg,
1578 getKillRegState(SrcIsKill));
1579
1580 MIBLO.setMemRefs(MI.memoperands());
1581 MIBHI.setMemRefs(MI.memoperands());
1582
1583 MI.eraseFromParent();
1584 return true;
1585}
1586
1587template <>
1588bool AVRExpandPseudoImpl::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {
1589 MachineInstr &MI = *MBBI;
1590 Register SrcLoReg, SrcHiReg;
1591 Register SrcReg = MI.getOperand(0).getReg();
1592 bool SrcIsKill = MI.getOperand(0).isKill();
1593 unsigned Flags = MI.getFlags();
1594 unsigned OpLo = AVR::PUSHRr;
1595 unsigned OpHi = AVR::PUSHRr;
1596 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1597
1598 // Low part
1599 buildMI(MBB, MBBI, OpLo)
1600 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1601 .setMIFlags(Flags);
1602
1603 // High part
1604 buildMI(MBB, MBBI, OpHi)
1605 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1606 .setMIFlags(Flags);
1607
1608 MI.eraseFromParent();
1609 return true;
1610}
1611
1612template <>
1613bool AVRExpandPseudoImpl::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
1614 MachineInstr &MI = *MBBI;
1615 Register DstLoReg, DstHiReg;
1616 Register DstReg = MI.getOperand(0).getReg();
1617 unsigned Flags = MI.getFlags();
1618 unsigned OpLo = AVR::POPRd;
1619 unsigned OpHi = AVR::POPRd;
1620 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1621
1622 buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
1623 buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
1624
1625 MI.eraseFromParent();
1626 return true;
1627}
1628
1629bool AVRExpandPseudoImpl::expandROLBRd(Block &MBB, BlockIt MBBI) {
1630 // In AVR, the rotate instructions behave quite unintuitively. They rotate
1631 // bits through the carry bit in SREG, effectively rotating over 9 bits,
1632 // instead of 8. This is useful when we are dealing with numbers over
1633 // multiple registers, but when we actually need to rotate stuff, we have
1634 // to explicitly add the carry bit.
1635
1636 MachineInstr &MI = *MBBI;
1637 unsigned OpShift, OpCarry;
1638 Register DstReg = MI.getOperand(0).getReg();
1639 Register ZeroReg = MI.getOperand(3).getReg();
1640 bool DstIsDead = MI.getOperand(0).isDead();
1641 bool DstIsKill = MI.getOperand(1).isKill();
1642 OpShift = AVR::ADDRdRr;
1643 OpCarry = AVR::ADCRdRr;
1644
1645 // add r16, r16
1646 // adc r16, r1
1647
1648 // Shift part
1649 buildMI(MBB, MBBI, OpShift)
1650 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1651 .addReg(DstReg, RegState::Kill)
1652 .addReg(DstReg, RegState::Kill);
1653
1654 // Add the carry bit
1655 auto MIB = buildMI(MBB, MBBI, OpCarry)
1656 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1657 .addReg(DstReg, getKillRegState(DstIsKill))
1658 .addReg(ZeroReg);
1659
1660 MIB->getOperand(3).setIsDead(); // SREG is always dead
1661 MIB->getOperand(4).setIsKill(); // SREG is always implicitly killed
1662
1663 MI.eraseFromParent();
1664 return true;
1665}
1666
1667template <>
1668bool AVRExpandPseudoImpl::expand<AVR::ROLBRdR1>(Block &MBB, BlockIt MBBI) {
1669 return expandROLBRd(MBB, MBBI);
1670}
1671
1672template <>
1673bool AVRExpandPseudoImpl::expand<AVR::ROLBRdR17>(Block &MBB, BlockIt MBBI) {
1674 return expandROLBRd(MBB, MBBI);
1675}
1676
1677template <>
1678bool AVRExpandPseudoImpl::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) {
1679 // In AVR, the rotate instructions behave quite unintuitively. They rotate
1680 // bits through the carry bit in SREG, effectively rotating over 9 bits,
1681 // instead of 8. This is useful when we are dealing with numbers over
1682 // multiple registers, but when we actually need to rotate stuff, we have
1683 // to explicitly add the carry bit.
1684
1685 MachineInstr &MI = *MBBI;
1686 Register DstReg = MI.getOperand(0).getReg();
1687
1688 // bst r16, 0
1689 // ror r16
1690 // bld r16, 7
1691
1692 // Move the lowest bit from DstReg into the T bit
1693 buildMI(MBB, MBBI, AVR::BST).addReg(DstReg).addImm(0);
1694
1695 // Rotate to the right
1696 buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg);
1697
1698 // Move the T bit into the highest bit of DstReg.
1699 buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7);
1700
1701 MI.eraseFromParent();
1702 return true;
1703}
1704
1705template <>
1706bool AVRExpandPseudoImpl::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
1707 MachineInstr &MI = *MBBI;
1708 Register DstLoReg, DstHiReg;
1709 Register DstReg = MI.getOperand(0).getReg();
1710 bool DstIsDead = MI.getOperand(0).isDead();
1711 bool DstIsKill = MI.getOperand(1).isKill();
1712 bool ImpIsDead = MI.getOperand(2).isDead();
1713 unsigned OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
1714 unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
1715 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1716
1717 // Low part
1718 buildMI(MBB, MBBI, OpLo)
1719 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1720 .addReg(DstLoReg, getKillRegState(DstIsKill))
1721 .addReg(DstLoReg, getKillRegState(DstIsKill));
1722
1723 auto MIBHI =
1724 buildMI(MBB, MBBI, OpHi)
1725 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1726 .addReg(DstHiReg, getKillRegState(DstIsKill))
1727 .addReg(DstHiReg, getKillRegState(DstIsKill));
1728
1729 if (ImpIsDead)
1730 MIBHI->getOperand(3).setIsDead();
1731
1732 // SREG is always implicitly killed
1733 MIBHI->getOperand(4).setIsKill();
1734
1735 MI.eraseFromParent();
1736 return true;
1737}
1738
1739template <>
1740bool AVRExpandPseudoImpl::expand<AVR::LSLWHiRd>(Block &MBB, BlockIt MBBI) {
1741 MachineInstr &MI = *MBBI;
1742 Register DstLoReg, DstHiReg;
1743 Register DstReg = MI.getOperand(0).getReg();
1744 bool DstIsDead = MI.getOperand(0).isDead();
1745 bool DstIsKill = MI.getOperand(1).isKill();
1746 bool ImpIsDead = MI.getOperand(2).isDead();
1747 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1748
1749 // add hireg, hireg <==> lsl hireg
1750 auto MILSL =
1751 buildMI(MBB, MBBI, AVR::ADDRdRr)
1752 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1753 .addReg(DstHiReg, getKillRegState(DstIsKill))
1754 .addReg(DstHiReg, getKillRegState(DstIsKill));
1755
1756 if (ImpIsDead)
1757 MILSL->getOperand(3).setIsDead();
1758
1759 MI.eraseFromParent();
1760 return true;
1761}
1762
1763bool AVRExpandPseudoImpl::expandLSLW4Rd(Block &MBB, BlockIt MBBI) {
1764 MachineInstr &MI = *MBBI;
1765 Register DstLoReg, DstHiReg;
1766 Register DstReg = MI.getOperand(0).getReg();
1767 bool DstIsDead = MI.getOperand(0).isDead();
1768 bool DstIsKill = MI.getOperand(1).isKill();
1769 bool ImpIsDead = MI.getOperand(3).isDead();
1770 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1771
1772 // swap Rh
1773 // swap Rl
1774 buildMI(MBB, MBBI, AVR::SWAPRd)
1775 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1776 .addReg(DstHiReg, RegState::Kill);
1777 buildMI(MBB, MBBI, AVR::SWAPRd)
1778 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1779 .addReg(DstLoReg, RegState::Kill);
1780
1781 // andi Rh, 0xf0
1782 auto MI0 =
1783 buildMI(MBB, MBBI, AVR::ANDIRdK)
1784 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1785 .addReg(DstHiReg, RegState::Kill)
1786 .addImm(0xf0);
1787 // SREG is implicitly dead.
1788 MI0->getOperand(3).setIsDead();
1789
1790 // eor Rh, Rl
1791 auto MI1 =
1792 buildMI(MBB, MBBI, AVR::EORRdRr)
1793 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1794 .addReg(DstHiReg, RegState::Kill)
1795 .addReg(DstLoReg);
1796 // SREG is implicitly dead.
1797 MI1->getOperand(3).setIsDead();
1798
1799 // andi Rl, 0xf0
1800 auto MI2 =
1801 buildMI(MBB, MBBI, AVR::ANDIRdK)
1802 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1803 .addReg(DstLoReg, getKillRegState(DstIsKill))
1804 .addImm(0xf0);
1805 // SREG is implicitly dead.
1806 MI2->getOperand(3).setIsDead();
1807
1808 // eor Rh, Rl
1809 auto MI3 =
1810 buildMI(MBB, MBBI, AVR::EORRdRr)
1811 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1812 .addReg(DstHiReg, getKillRegState(DstIsKill))
1813 .addReg(DstLoReg);
1814 if (ImpIsDead)
1815 MI3->getOperand(3).setIsDead();
1816
1817 MI.eraseFromParent();
1818 return true;
1819}
1820
1821bool AVRExpandPseudoImpl::expandLSLW8Rd(Block &MBB, BlockIt MBBI) {
1822 MachineInstr &MI = *MBBI;
1823 Register DstLoReg, DstHiReg;
1824 Register DstReg = MI.getOperand(0).getReg();
1825 bool DstIsDead = MI.getOperand(0).isDead();
1826 bool DstIsKill = MI.getOperand(1).isKill();
1827 bool ImpIsDead = MI.getOperand(3).isDead();
1828 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1829
1830 // mov Rh, Rl
1831 buildMI(MBB, MBBI, AVR::MOVRdRr)
1832 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1833 .addReg(DstLoReg);
1834
1835 // clr Rl
1836 auto MIBLO =
1837 buildMI(MBB, MBBI, AVR::EORRdRr)
1838 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1839 .addReg(DstLoReg, getKillRegState(DstIsKill))
1840 .addReg(DstLoReg, getKillRegState(DstIsKill));
1841 if (ImpIsDead)
1842 MIBLO->getOperand(3).setIsDead();
1843
1844 MI.eraseFromParent();
1845 return true;
1846}
1847
1848bool AVRExpandPseudoImpl::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
1849 MachineInstr &MI = *MBBI;
1850 Register DstLoReg, DstHiReg;
1851 Register DstReg = MI.getOperand(0).getReg();
1852 bool DstIsDead = MI.getOperand(0).isDead();
1853 bool DstIsKill = MI.getOperand(1).isKill();
1854 bool ImpIsDead = MI.getOperand(3).isDead();
1855 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1856
1857 // mov Rh, Rl
1858 buildMI(MBB, MBBI, AVR::MOVRdRr)
1859 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1860 .addReg(DstLoReg);
1861
1862 // swap Rh
1863 buildMI(MBB, MBBI, AVR::SWAPRd)
1864 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1865 .addReg(DstHiReg, RegState::Kill);
1866
1867 // andi Rh, 0xf0
1868 auto MI0 =
1869 buildMI(MBB, MBBI, AVR::ANDIRdK)
1870 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1871 .addReg(DstHiReg, getKillRegState(DstIsKill))
1872 .addImm(0xf0);
1873 // SREG is implicitly dead.
1874 MI0->getOperand(3).setIsDead();
1875
1876 // clr Rl
1877 auto MI1 =
1878 buildMI(MBB, MBBI, AVR::EORRdRr)
1879 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1880 .addReg(DstLoReg, getKillRegState(DstIsKill))
1881 .addReg(DstLoReg, getKillRegState(DstIsKill));
1882 if (ImpIsDead)
1883 MI1->getOperand(3).setIsDead();
1884
1885 MI.eraseFromParent();
1886 return true;
1887}
1888
1889template <>
1890bool AVRExpandPseudoImpl::expand<AVR::LSLWNRd>(Block &MBB, BlockIt MBBI) {
1891 MachineInstr &MI = *MBBI;
1892 unsigned Imm = MI.getOperand(2).getImm();
1893 switch (Imm) {
1894 case 4:
1895 return expandLSLW4Rd(MBB, MBBI);
1896 case 8:
1897 return expandLSLW8Rd(MBB, MBBI);
1898 case 12:
1899 return expandLSLW12Rd(MBB, MBBI);
1900 default:
1901 llvm_unreachable("unimplemented lslwn");
1902 return false;
1903 }
1904}
1905
1906template <>
1907bool AVRExpandPseudoImpl::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
1908 MachineInstr &MI = *MBBI;
1909 Register DstLoReg, DstHiReg;
1910 Register DstReg = MI.getOperand(0).getReg();
1911 bool DstIsDead = MI.getOperand(0).isDead();
1912 bool DstIsKill = MI.getOperand(1).isKill();
1913 bool ImpIsDead = MI.getOperand(2).isDead();
1914 unsigned OpLo = AVR::RORRd;
1915 unsigned OpHi = AVR::LSRRd;
1916 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1917
1918 // High part
1919 buildMI(MBB, MBBI, OpHi)
1920 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1921 .addReg(DstHiReg, getKillRegState(DstIsKill));
1922
1923 auto MIBLO =
1924 buildMI(MBB, MBBI, OpLo)
1925 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1926 .addReg(DstLoReg, getKillRegState(DstIsKill));
1927
1928 if (ImpIsDead)
1929 MIBLO->getOperand(2).setIsDead();
1930
1931 // SREG is always implicitly killed
1932 MIBLO->getOperand(3).setIsKill();
1933
1934 MI.eraseFromParent();
1935 return true;
1936}
1937
1938template <>
1939bool AVRExpandPseudoImpl::expand<AVR::LSRWLoRd>(Block &MBB, BlockIt MBBI) {
1940 MachineInstr &MI = *MBBI;
1941 Register DstLoReg, DstHiReg;
1942 Register DstReg = MI.getOperand(0).getReg();
1943 bool DstIsDead = MI.getOperand(0).isDead();
1944 bool DstIsKill = MI.getOperand(1).isKill();
1945 bool ImpIsDead = MI.getOperand(2).isDead();
1946 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1947
1948 // lsr loreg
1949 auto MILSR =
1950 buildMI(MBB, MBBI, AVR::LSRRd)
1951 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1952 .addReg(DstLoReg, getKillRegState(DstIsKill));
1953
1954 if (ImpIsDead)
1955 MILSR->getOperand(2).setIsDead();
1956
1957 MI.eraseFromParent();
1958 return true;
1959}
1960
1961bool AVRExpandPseudoImpl::expandLSRW4Rd(Block &MBB, BlockIt MBBI) {
1962 MachineInstr &MI = *MBBI;
1963 Register DstLoReg, DstHiReg;
1964 Register DstReg = MI.getOperand(0).getReg();
1965 bool DstIsDead = MI.getOperand(0).isDead();
1966 bool DstIsKill = MI.getOperand(1).isKill();
1967 bool ImpIsDead = MI.getOperand(3).isDead();
1968 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1969
1970 // swap Rh
1971 // swap Rl
1972 buildMI(MBB, MBBI, AVR::SWAPRd)
1973 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1974 .addReg(DstHiReg, RegState::Kill);
1975 buildMI(MBB, MBBI, AVR::SWAPRd)
1976 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1977 .addReg(DstLoReg, RegState::Kill);
1978
1979 // andi Rl, 0xf
1980 auto MI0 =
1981 buildMI(MBB, MBBI, AVR::ANDIRdK)
1982 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1983 .addReg(DstLoReg, RegState::Kill)
1984 .addImm(0xf);
1985 // SREG is implicitly dead.
1986 MI0->getOperand(3).setIsDead();
1987
1988 // eor Rl, Rh
1989 auto MI1 =
1990 buildMI(MBB, MBBI, AVR::EORRdRr)
1991 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1992 .addReg(DstLoReg, RegState::Kill)
1993 .addReg(DstHiReg);
1994 // SREG is implicitly dead.
1995 MI1->getOperand(3).setIsDead();
1996
1997 // andi Rh, 0xf
1998 auto MI2 =
1999 buildMI(MBB, MBBI, AVR::ANDIRdK)
2000 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2001 .addReg(DstHiReg, getKillRegState(DstIsKill))
2002 .addImm(0xf);
2003 // SREG is implicitly dead.
2004 MI2->getOperand(3).setIsDead();
2005
2006 // eor Rl, Rh
2007 auto MI3 =
2008 buildMI(MBB, MBBI, AVR::EORRdRr)
2009 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2010 .addReg(DstLoReg, getKillRegState(DstIsKill))
2011 .addReg(DstHiReg);
2012 if (ImpIsDead)
2013 MI3->getOperand(3).setIsDead();
2014
2015 MI.eraseFromParent();
2016 return true;
2017}
2018
2019bool AVRExpandPseudoImpl::expandLSRW8Rd(Block &MBB, BlockIt MBBI) {
2020 MachineInstr &MI = *MBBI;
2021 Register DstLoReg, DstHiReg;
2022 Register DstReg = MI.getOperand(0).getReg();
2023 bool DstIsDead = MI.getOperand(0).isDead();
2024 bool DstIsKill = MI.getOperand(1).isKill();
2025 bool ImpIsDead = MI.getOperand(3).isDead();
2026 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2027
2028 // Move upper byte to lower byte.
2029 buildMI(MBB, MBBI, AVR::MOVRdRr)
2030 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2031 .addReg(DstHiReg);
2032
2033 // Clear upper byte.
2034 auto MIBHI =
2035 buildMI(MBB, MBBI, AVR::EORRdRr)
2036 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2037 .addReg(DstHiReg, getKillRegState(DstIsKill))
2038 .addReg(DstHiReg, getKillRegState(DstIsKill));
2039 if (ImpIsDead)
2040 MIBHI->getOperand(3).setIsDead();
2041
2042 MI.eraseFromParent();
2043 return true;
2044}
2045
2046bool AVRExpandPseudoImpl::expandLSRW12Rd(Block &MBB, BlockIt MBBI) {
2047 MachineInstr &MI = *MBBI;
2048 Register DstLoReg, DstHiReg;
2049 Register DstReg = MI.getOperand(0).getReg();
2050 bool DstIsDead = MI.getOperand(0).isDead();
2051 bool DstIsKill = MI.getOperand(1).isKill();
2052 bool ImpIsDead = MI.getOperand(3).isDead();
2053 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2054
2055 // Move upper byte to lower byte.
2056 buildMI(MBB, MBBI, AVR::MOVRdRr)
2057 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2058 .addReg(DstHiReg);
2059
2060 // swap Rl
2061 buildMI(MBB, MBBI, AVR::SWAPRd)
2062 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2063 .addReg(DstLoReg, RegState::Kill);
2064
2065 // andi Rl, 0xf
2066 auto MI0 =
2067 buildMI(MBB, MBBI, AVR::ANDIRdK)
2068 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2069 .addReg(DstLoReg, getKillRegState(DstIsKill))
2070 .addImm(0xf);
2071 // SREG is implicitly dead.
2072 MI0->getOperand(3).setIsDead();
2073
2074 // Clear upper byte.
2075 auto MIBHI =
2076 buildMI(MBB, MBBI, AVR::EORRdRr)
2077 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2078 .addReg(DstHiReg, getKillRegState(DstIsKill))
2079 .addReg(DstHiReg, getKillRegState(DstIsKill));
2080 if (ImpIsDead)
2081 MIBHI->getOperand(3).setIsDead();
2082
2083 MI.eraseFromParent();
2084 return true;
2085}
2086
2087template <>
2088bool AVRExpandPseudoImpl::expand<AVR::LSRWNRd>(Block &MBB, BlockIt MBBI) {
2089 MachineInstr &MI = *MBBI;
2090 unsigned Imm = MI.getOperand(2).getImm();
2091 switch (Imm) {
2092 case 4:
2093 return expandLSRW4Rd(MBB, MBBI);
2094 case 8:
2095 return expandLSRW8Rd(MBB, MBBI);
2096 case 12:
2097 return expandLSRW12Rd(MBB, MBBI);
2098 default:
2099 llvm_unreachable("unimplemented lsrwn");
2100 return false;
2101 }
2102}
2103
2104template <>
2105bool AVRExpandPseudoImpl::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
2106 llvm_unreachable("RORW unimplemented");
2107 return false;
2108}
2109
2110template <>
2111bool AVRExpandPseudoImpl::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) {
2112 llvm_unreachable("ROLW unimplemented");
2113 return false;
2114}
2115
2116template <>
2117bool AVRExpandPseudoImpl::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
2118 MachineInstr &MI = *MBBI;
2119 Register DstLoReg, DstHiReg;
2120 Register DstReg = MI.getOperand(0).getReg();
2121 bool DstIsDead = MI.getOperand(0).isDead();
2122 bool DstIsKill = MI.getOperand(1).isKill();
2123 bool ImpIsDead = MI.getOperand(2).isDead();
2124 unsigned OpLo = AVR::RORRd;
2125 unsigned OpHi = AVR::ASRRd;
2126 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2127
2128 // High part
2129 buildMI(MBB, MBBI, OpHi)
2130 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2131 .addReg(DstHiReg, getKillRegState(DstIsKill));
2132
2133 auto MIBLO =
2134 buildMI(MBB, MBBI, OpLo)
2135 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2136 .addReg(DstLoReg, getKillRegState(DstIsKill));
2137
2138 if (ImpIsDead)
2139 MIBLO->getOperand(2).setIsDead();
2140
2141 // SREG is always implicitly killed
2142 MIBLO->getOperand(3).setIsKill();
2143
2144 MI.eraseFromParent();
2145 return true;
2146}
2147
2148template <>
2149bool AVRExpandPseudoImpl::expand<AVR::ASRWLoRd>(Block &MBB, BlockIt MBBI) {
2150 MachineInstr &MI = *MBBI;
2151 Register DstLoReg, DstHiReg;
2152 Register DstReg = MI.getOperand(0).getReg();
2153 bool DstIsDead = MI.getOperand(0).isDead();
2154 bool DstIsKill = MI.getOperand(1).isKill();
2155 bool ImpIsDead = MI.getOperand(2).isDead();
2156 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2157
2158 // asr loreg
2159 auto MIASR =
2160 buildMI(MBB, MBBI, AVR::ASRRd)
2161 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2162 .addReg(DstLoReg, getKillRegState(DstIsKill));
2163
2164 if (ImpIsDead)
2165 MIASR->getOperand(2).setIsDead();
2166
2167 MI.eraseFromParent();
2168 return true;
2169}
2170
2171bool AVRExpandPseudoImpl::expandASRW7Rd(Block &MBB, BlockIt MBBI) {
2172 MachineInstr &MI = *MBBI;
2173 Register DstLoReg, DstHiReg;
2174 Register DstReg = MI.getOperand(0).getReg();
2175 bool DstIsDead = MI.getOperand(0).isDead();
2176 bool DstIsKill = MI.getOperand(1).isKill();
2177 bool ImpIsDead = MI.getOperand(3).isDead();
2178 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2179
2180 // lsl r24
2181 // mov r24,r25
2182 // rol r24
2183 // sbc r25,r25
2184
2185 // lsl r24 <=> add r24, r24
2186 buildMI(MBB, MBBI, AVR::ADDRdRr)
2187 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2188 .addReg(DstLoReg, RegState::Kill)
2189 .addReg(DstLoReg, RegState::Kill);
2190
2191 // mov r24, r25
2192 buildMI(MBB, MBBI, AVR::MOVRdRr)
2193 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2194 .addReg(DstHiReg);
2195
2196 // rol r24 <=> adc r24, r24
2197 buildMI(MBB, MBBI, AVR::ADCRdRr)
2198 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2199 .addReg(DstLoReg, getKillRegState(DstIsKill))
2200 .addReg(DstLoReg, getKillRegState(DstIsKill));
2201
2202 // sbc r25, r25
2203 auto MISBC =
2204 buildMI(MBB, MBBI, AVR::SBCRdRr)
2205 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2206 .addReg(DstHiReg, getKillRegState(DstIsKill))
2207 .addReg(DstHiReg, getKillRegState(DstIsKill));
2208
2209 if (ImpIsDead)
2210 MISBC->getOperand(3).setIsDead();
2211 // SREG is always implicitly killed
2212 MISBC->getOperand(4).setIsKill();
2213
2214 MI.eraseFromParent();
2215 return true;
2216}
2217
2218bool AVRExpandPseudoImpl::expandASRW8Rd(Block &MBB, BlockIt MBBI) {
2219 MachineInstr &MI = *MBBI;
2220 Register DstLoReg, DstHiReg;
2221 Register DstReg = MI.getOperand(0).getReg();
2222 bool DstIsDead = MI.getOperand(0).isDead();
2223 bool DstIsKill = MI.getOperand(1).isKill();
2224 bool ImpIsDead = MI.getOperand(3).isDead();
2225 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2226
2227 // Move upper byte to lower byte.
2228 buildMI(MBB, MBBI, AVR::MOVRdRr)
2229 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2230 .addReg(DstHiReg);
2231
2232 // Move the sign bit to the C flag.
2233 buildMI(MBB, MBBI, AVR::ADDRdRr)
2234 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2235 .addReg(DstHiReg, RegState::Kill)
2236 .addReg(DstHiReg, RegState::Kill);
2237
2238 // Set upper byte to 0 or -1.
2239 auto MIBHI =
2240 buildMI(MBB, MBBI, AVR::SBCRdRr)
2241 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2242 .addReg(DstHiReg, getKillRegState(DstIsKill))
2243 .addReg(DstHiReg, getKillRegState(DstIsKill));
2244
2245 if (ImpIsDead)
2246 MIBHI->getOperand(3).setIsDead();
2247 // SREG is always implicitly killed
2248 MIBHI->getOperand(4).setIsKill();
2249
2250 MI.eraseFromParent();
2251 return true;
2252}
2253bool AVRExpandPseudoImpl::expandASRW14Rd(Block &MBB, BlockIt MBBI) {
2254 MachineInstr &MI = *MBBI;
2255 Register DstLoReg, DstHiReg;
2256 Register DstReg = MI.getOperand(0).getReg();
2257 bool DstIsDead = MI.getOperand(0).isDead();
2258 bool DstIsKill = MI.getOperand(1).isKill();
2259 bool ImpIsDead = MI.getOperand(3).isDead();
2260 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2261
2262 // lsl r25
2263 // sbc r24, r24
2264 // lsl r25
2265 // mov r25, r24
2266 // rol r24
2267
2268 // lsl r25 <=> add r25, r25
2269 buildMI(MBB, MBBI, AVR::ADDRdRr)
2270 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2271 .addReg(DstHiReg, RegState::Kill)
2272 .addReg(DstHiReg, RegState::Kill);
2273
2274 // sbc r24, r24
2275 buildMI(MBB, MBBI, AVR::SBCRdRr)
2276 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2277 .addReg(DstLoReg, RegState::Kill)
2278 .addReg(DstLoReg, RegState::Kill);
2279
2280 // lsl r25 <=> add r25, r25
2281 buildMI(MBB, MBBI, AVR::ADDRdRr)
2282 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2283 .addReg(DstHiReg, RegState::Kill)
2284 .addReg(DstHiReg, RegState::Kill);
2285
2286 // mov r25, r24
2287 buildMI(MBB, MBBI, AVR::MOVRdRr)
2288 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2289 .addReg(DstLoReg);
2290
2291 // rol r24 <=> adc r24, r24
2292 auto MIROL =
2293 buildMI(MBB, MBBI, AVR::ADCRdRr)
2294 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2295 .addReg(DstLoReg, getKillRegState(DstIsKill))
2296 .addReg(DstLoReg, getKillRegState(DstIsKill));
2297
2298 if (ImpIsDead)
2299 MIROL->getOperand(3).setIsDead();
2300 // SREG is always implicitly killed
2301 MIROL->getOperand(4).setIsKill();
2302
2303 MI.eraseFromParent();
2304 return false;
2305}
2306
2307bool AVRExpandPseudoImpl::expandASRW15Rd(Block &MBB, BlockIt MBBI) {
2308 MachineInstr &MI = *MBBI;
2309 Register DstLoReg, DstHiReg;
2310 Register DstReg = MI.getOperand(0).getReg();
2311 bool DstIsDead = MI.getOperand(0).isDead();
2312 bool ImpIsDead = MI.getOperand(3).isDead();
2313 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2314
2315 // lsl r25
2316 // sbc r25, r25
2317 // mov r24, r25
2318
2319 // lsl r25 <=> add r25, r25
2320 buildMI(MBB, MBBI, AVR::ADDRdRr)
2321 .addReg(DstHiReg, RegState::Define)
2322 .addReg(DstHiReg, RegState::Kill)
2323 .addReg(DstHiReg, RegState::Kill);
2324
2325 // sbc r25, r25
2326 auto MISBC =
2327 buildMI(MBB, MBBI, AVR::SBCRdRr)
2328 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2329 .addReg(DstHiReg, RegState::Kill)
2330 .addReg(DstHiReg, RegState::Kill);
2331 if (ImpIsDead)
2332 MISBC->getOperand(3).setIsDead();
2333 // SREG is always implicitly killed
2334 MISBC->getOperand(4).setIsKill();
2335
2336 // mov r24, r25
2337 buildMI(MBB, MBBI, AVR::MOVRdRr)
2338 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2339 .addReg(DstHiReg);
2340
2341 MI.eraseFromParent();
2342 return true;
2343}
2344
2345template <>
2346bool AVRExpandPseudoImpl::expand<AVR::ASRWNRd>(Block &MBB, BlockIt MBBI) {
2347 MachineInstr &MI = *MBBI;
2348 unsigned Imm = MI.getOperand(2).getImm();
2349 switch (Imm) {
2350 case 7:
2351 return expandASRW7Rd(MBB, MBBI);
2352 case 8:
2353 return expandASRW8Rd(MBB, MBBI);
2354 case 14:
2355 return expandASRW14Rd(MBB, MBBI);
2356 case 15:
2357 return expandASRW15Rd(MBB, MBBI);
2358 default:
2359 llvm_unreachable("unimplemented asrwn");
2360 return false;
2361 }
2362}
2363
2364bool AVRExpandPseudoImpl::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
2365 MachineInstr &MI = *MBBI;
2366 Register DstReg = MI.getOperand(0).getReg();
2367 bool DstIsDead = MI.getOperand(0).isDead();
2368 bool DstIsKill = MI.getOperand(1).isKill();
2369 bool ImpIsDead = MI.getOperand(3).isDead();
2370
2371 // ror r24
2372 // clr r24
2373 // ror r24
2374
2375 buildMI(MBB, MBBI, AVR::RORRd)
2376 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2377 .addReg(DstReg, RegState::Kill)
2378 ->getOperand(3)
2379 .setIsUndef(true);
2380
2381 buildMI(MBB, MBBI, AVR::EORRdRr)
2382 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2383 .addReg(DstReg, RegState::Kill)
2384 .addReg(DstReg, RegState::Kill);
2385
2386 auto MIRRC =
2387 buildMI(MBB, MBBI, AVR::RORRd)
2388 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2389 .addReg(DstReg, getKillRegState(DstIsKill));
2390
2391 if (ImpIsDead)
2392 MIRRC->getOperand(2).setIsDead();
2393
2394 // SREG is always implicitly killed
2395 MIRRC->getOperand(3).setIsKill();
2396
2397 MI.eraseFromParent();
2398 return true;
2399}
2400
2401template <>
2402bool AVRExpandPseudoImpl::expand<AVR::LSLBNRd>(Block &MBB, BlockIt MBBI) {
2403 MachineInstr &MI = *MBBI;
2404 unsigned Imm = MI.getOperand(2).getImm();
2405 switch (Imm) {
2406 case 7:
2407 return expandLSLB7Rd(MBB, MBBI);
2408 default:
2409 llvm_unreachable("unimplemented lslbn");
2410 return false;
2411 }
2412}
2413
2414bool AVRExpandPseudoImpl::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
2415 MachineInstr &MI = *MBBI;
2416 Register DstReg = MI.getOperand(0).getReg();
2417 bool DstIsDead = MI.getOperand(0).isDead();
2418 bool DstIsKill = MI.getOperand(1).isKill();
2419 bool ImpIsDead = MI.getOperand(3).isDead();
2420
2421 // rol r24
2422 // clr r24
2423 // rol r24
2424
2425 buildMI(MBB, MBBI, AVR::ADCRdRr)
2426 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2427 .addReg(DstReg, RegState::Kill)
2428 .addReg(DstReg, RegState::Kill)
2429 ->getOperand(4)
2430 .setIsUndef(true);
2431
2432 buildMI(MBB, MBBI, AVR::EORRdRr)
2433 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2434 .addReg(DstReg, RegState::Kill)
2435 .addReg(DstReg, RegState::Kill);
2436
2437 auto MIRRC =
2438 buildMI(MBB, MBBI, AVR::ADCRdRr)
2439 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2440 .addReg(DstReg, getKillRegState(DstIsKill))
2441 .addReg(DstReg, getKillRegState(DstIsKill));
2442
2443 if (ImpIsDead)
2444 MIRRC->getOperand(3).setIsDead();
2445
2446 // SREG is always implicitly killed
2447 MIRRC->getOperand(4).setIsKill();
2448
2449 MI.eraseFromParent();
2450 return true;
2451}
2452
2453template <>
2454bool AVRExpandPseudoImpl::expand<AVR::LSRBNRd>(Block &MBB, BlockIt MBBI) {
2455 MachineInstr &MI = *MBBI;
2456 unsigned Imm = MI.getOperand(2).getImm();
2457 switch (Imm) {
2458 case 7:
2459 return expandLSRB7Rd(MBB, MBBI);
2460 default:
2461 llvm_unreachable("unimplemented lsrbn");
2462 return false;
2463 }
2464}
2465
2466bool AVRExpandPseudoImpl::expandASRB6Rd(Block &MBB, BlockIt MBBI) {
2467 MachineInstr &MI = *MBBI;
2468 Register DstReg = MI.getOperand(0).getReg();
2469 bool DstIsDead = MI.getOperand(0).isDead();
2470 bool DstIsKill = MI.getOperand(1).isKill();
2471
2472 // bst r24, 6
2473 // lsl r24
2474 // sbc r24, r24
2475 // bld r24, 0
2476
2477 buildMI(MBB, MBBI, AVR::BST)
2478 .addReg(DstReg)
2479 .addImm(6)
2480 ->getOperand(2)
2481 .setIsUndef(true);
2482
2483 buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rd
2484 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2485 .addReg(DstReg, RegState::Kill)
2486 .addReg(DstReg, RegState::Kill);
2487
2488 buildMI(MBB, MBBI, AVR::SBCRdRr)
2489 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2490 .addReg(DstReg, RegState::Kill)
2491 .addReg(DstReg, RegState::Kill);
2492
2493 buildMI(MBB, MBBI, AVR::BLD)
2494 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2495 .addReg(DstReg, getKillRegState(DstIsKill))
2496 .addImm(0)
2497 ->getOperand(3)
2498 .setIsKill();
2499
2500 MI.eraseFromParent();
2501 return true;
2502}
2503
2504bool AVRExpandPseudoImpl::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
2505 MachineInstr &MI = *MBBI;
2506 Register DstReg = MI.getOperand(0).getReg();
2507 bool DstIsDead = MI.getOperand(0).isDead();
2508 bool DstIsKill = MI.getOperand(1).isKill();
2509 bool ImpIsDead = MI.getOperand(3).isDead();
2510
2511 // lsl r24
2512 // sbc r24, r24
2513
2514 buildMI(MBB, MBBI, AVR::ADDRdRr)
2515 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2516 .addReg(DstReg, RegState::Kill)
2517 .addReg(DstReg, RegState::Kill);
2518
2519 auto MIRRC =
2520 buildMI(MBB, MBBI, AVR::SBCRdRr)
2521 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2522 .addReg(DstReg, getKillRegState(DstIsKill))
2523 .addReg(DstReg, getKillRegState(DstIsKill));
2524
2525 if (ImpIsDead)
2526 MIRRC->getOperand(3).setIsDead();
2527
2528 // SREG is always implicitly killed
2529 MIRRC->getOperand(4).setIsKill();
2530
2531 MI.eraseFromParent();
2532 return true;
2533}
2534
2535template <>
2536bool AVRExpandPseudoImpl::expand<AVR::ASRBNRd>(Block &MBB, BlockIt MBBI) {
2537 MachineInstr &MI = *MBBI;
2538 unsigned Imm = MI.getOperand(2).getImm();
2539 switch (Imm) {
2540 case 6:
2541 return expandASRB6Rd(MBB, MBBI);
2542 case 7:
2543 return expandASRB7Rd(MBB, MBBI);
2544 default:
2545 llvm_unreachable("unimplemented asrbn");
2546 return false;
2547 }
2548}
2549
2550template <>
2551bool AVRExpandPseudoImpl::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
2552 MachineInstr &MI = *MBBI;
2553 Register DstLoReg, DstHiReg;
2554 // sext R17:R16, R17
2555 // mov r16, r17
2556 // lsl r17
2557 // sbc r17, r17
2558 // sext R17:R16, R13
2559 // mov r16, r13
2560 // mov r17, r13
2561 // lsl r17
2562 // sbc r17, r17
2563 // sext R17:R16, R16
2564 // mov r17, r16
2565 // lsl r17
2566 // sbc r17, r17
2567 Register DstReg = MI.getOperand(0).getReg();
2568 Register SrcReg = MI.getOperand(1).getReg();
2569 bool DstIsDead = MI.getOperand(0).isDead();
2570 bool SrcIsKill = MI.getOperand(1).isKill();
2571 bool ImpIsDead = MI.getOperand(2).isDead();
2572 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2573
2574 if (SrcReg != DstLoReg)
2575 buildMI(MBB, MBBI, AVR::MOVRdRr)
2576 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2577 .addReg(SrcReg);
2578
2579 if (SrcReg != DstHiReg) {
2580 auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
2581 .addReg(DstHiReg, RegState::Define)
2582 .addReg(SrcReg);
2583 if (SrcReg != DstLoReg && SrcIsKill)
2584 MOV->getOperand(1).setIsKill();
2585 }
2586
2587 buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
2588 .addReg(DstHiReg, RegState::Define)
2589 .addReg(DstHiReg, RegState::Kill)
2590 .addReg(DstHiReg, RegState::Kill);
2591
2592 auto SBC =
2593 buildMI(MBB, MBBI, AVR::SBCRdRr)
2594 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2595 .addReg(DstHiReg, RegState::Kill)
2596 .addReg(DstHiReg, RegState::Kill);
2597
2598 if (ImpIsDead)
2599 SBC->getOperand(3).setIsDead();
2600
2601 // SREG is always implicitly killed
2602 SBC->getOperand(4).setIsKill();
2603
2604 MI.eraseFromParent();
2605 return true;
2606}
2607
2608template <>
2609bool AVRExpandPseudoImpl::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
2610 MachineInstr &MI = *MBBI;
2611 Register DstLoReg, DstHiReg;
2612 // zext R25:R24, R20
2613 // mov R24, R20
2614 // eor R25, R25
2615 // zext R25:R24, R24
2616 // eor R25, R25
2617 // zext R25:R24, R25
2618 // mov R24, R25
2619 // eor R25, R25
2620 Register DstReg = MI.getOperand(0).getReg();
2621 Register SrcReg = MI.getOperand(1).getReg();
2622 bool DstIsDead = MI.getOperand(0).isDead();
2623 bool SrcIsKill = MI.getOperand(1).isKill();
2624 bool ImpIsDead = MI.getOperand(2).isDead();
2625 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2626
2627 if (SrcReg != DstLoReg) {
2628 buildMI(MBB, MBBI, AVR::MOVRdRr)
2629 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2630 .addReg(SrcReg, getKillRegState(SrcIsKill));
2631 }
2632
2633 auto EOR =
2634 buildMI(MBB, MBBI, AVR::EORRdRr)
2635 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2636 .addReg(DstHiReg, RegState::Kill | RegState::Undef)
2637 .addReg(DstHiReg, RegState::Kill | RegState::Undef);
2638
2639 if (ImpIsDead)
2640 EOR->getOperand(3).setIsDead();
2641
2642 MI.eraseFromParent();
2643 return true;
2644}
2645
2646template <>
2647bool AVRExpandPseudoImpl::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
2648 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
2649 MachineInstr &MI = *MBBI;
2650 Register DstLoReg, DstHiReg;
2651 Register DstReg = MI.getOperand(0).getReg();
2652 bool DstIsDead = MI.getOperand(0).isDead();
2653 unsigned Flags = MI.getFlags();
2654 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2655
2656 // Low part
2657 buildMI(MBB, MBBI, AVR::INRdA)
2658 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2659 .addImm(STI.getIORegSPL())
2660 .setMIFlags(Flags);
2661
2662 // High part
2663 if (STI.getIORegSPH() != -1) {
2664 buildMI(MBB, MBBI, AVR::INRdA)
2665 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2666 .addImm(STI.getIORegSPH())
2667 .setMIFlags(Flags);
2668 } else {
2669 // Clear the upper byte if there is no SPH.
2670 auto MI0 =
2671 buildMI(MBB, MBBI, AVR::EORRdRr)
2672 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2673 .addReg(DstHiReg, RegState::Kill | RegState::Undef)
2674 .addReg(DstHiReg, RegState::Kill | RegState::Undef);
2675
2676 // SREG is implicitly dead.
2677 MI0->getOperand(3).setIsDead();
2678 }
2679
2680 MI.eraseFromParent();
2681 return true;
2682}
2683
2684template <>
2685bool AVRExpandPseudoImpl::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
2686 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
2687 MachineInstr &MI = *MBBI;
2688 Register SrcLoReg, SrcHiReg;
2689 Register SrcReg = MI.getOperand(1).getReg();
2690 bool SrcIsKill = MI.getOperand(1).isKill();
2691 unsigned Flags = MI.getFlags();
2692 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
2693
2694 // From the XMEGA series manual:
2695 // To prevent corruption when updating the stack pointer from software,
2696 // a write to SPL will automatically disable interrupts
2697 // for up to four instructions or until the next I/O memory write.
2698 if (STI.getELFArch() >= 102) { // An XMEGA device
2699 buildMI(MBB, MBBI, AVR::OUTARr)
2700 .addImm(STI.getIORegSPL())
2701 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2702 .setMIFlags(Flags);
2703
2704 buildMI(MBB, MBBI, AVR::OUTARr)
2705 .addImm(STI.getIORegSPH())
2706 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2707 .setMIFlags(Flags);
2708 } else { // Disable interrupts for older devices with SPH (3 extra
2709 // instructions)
2710 if (STI.getIORegSPH() != -1) {
2711 buildMI(MBB, MBBI, AVR::INRdA)
2712 .addReg(STI.getTmpRegister(), RegState::Define)
2713 .addImm(STI.getIORegSREG())
2714 .setMIFlags(Flags);
2715
2716 buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
2717
2718 buildMI(MBB, MBBI, AVR::OUTARr)
2719 .addImm(STI.getIORegSPH())
2720 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2721 .setMIFlags(Flags);
2722
2723 buildMI(MBB, MBBI, AVR::OUTARr)
2724 .addImm(STI.getIORegSREG())
2725 .addReg(STI.getTmpRegister(), RegState::Kill)
2726 .setMIFlags(Flags);
2727 }
2728
2729 buildMI(MBB, MBBI, AVR::OUTARr)
2730 .addImm(STI.getIORegSPL())
2731 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2732 .setMIFlags(Flags);
2733 }
2734
2735 MI.eraseFromParent();
2736 return true;
2737}
2738
2739template <>
2740bool AVRExpandPseudoImpl::expand<AVR::FRMSP>(Block &MBB, BlockIt MBBI) {
2741 MachineInstr &MI = *MBBI;
2742 MachineFunction &MF = *MI.getMF();
2743 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
2744 DebugLoc DL;
2745 Register ASOPointer = MI.getOperand(0).getReg();
2746 int64_t ASOAlignment = MI.getOperand(1).getImm();
2747
2748 // Note: `FrameReg` is an out-param here - passing `ASOPointer` instead would
2749 // overwrite the register we are supposed to write the aligned stack address
2750 // into.
2751 Register FrameReg;
2752
2753 StackOffset ASOOffset =
2754 MF.getSubtarget<AVRSubtarget>()
2755 .getFrameLowering()
2756 ->getFrameIndexReference(MF, AFI->AlignedStackObjectIdx, FrameReg);
2757
2758 TII->copyPhysReg(MBB, MI, DL, ASOPointer, AVR::R29R28, false, false, false);
2759
2760 buildMI(MBB, MI, AVR::ADIWRdKP)
2761 .addReg(ASOPointer, RegState::Define)
2762 .addReg(ASOPointer, RegState::Kill)
2763 .addImm(ASOOffset.getFixed() + ASOAlignment - 1)
2764 .setOperandDead(3); // implicit-def $sreg
2765
2766 buildMI(MBB, MI, AVR::ANDIWRdK)
2767 .addReg(ASOPointer, RegState::Define)
2768 .addReg(ASOPointer, RegState::Kill)
2769 .addImm(-ASOAlignment)
2770 .setOperandDead(3); // implicit-def $sreg
2771
2772 MI.eraseFromParent();
2773 return true;
2774}
2775
2776bool AVRExpandPseudoImpl::expandMI(Block &MBB, BlockIt MBBI) {
2777 MachineInstr &MI = *MBBI;
2778 int Opcode = MBBI->getOpcode();
2779
2780#define EXPAND(Op) \
2781 case Op: \
2782 return expand<Op>(MBB, MI)
2783
2784 switch (Opcode) {
2785 EXPAND(AVR::ADDWRdRr);
2786 EXPAND(AVR::ADCWRdRr);
2787 EXPAND(AVR::ADIWRdKP);
2788 EXPAND(AVR::SUBWRdRr);
2789 EXPAND(AVR::SUBIWRdK);
2790 EXPAND(AVR::SBCWRdRr);
2791 EXPAND(AVR::SBCIWRdK);
2792 EXPAND(AVR::ANDWRdRr);
2793 EXPAND(AVR::ANDIWRdK);
2794 EXPAND(AVR::ORWRdRr);
2795 EXPAND(AVR::ORIWRdK);
2796 EXPAND(AVR::EORWRdRr);
2797 EXPAND(AVR::COMWRd);
2798 EXPAND(AVR::NEGWRd);
2799 EXPAND(AVR::CPWRdRr);
2800 EXPAND(AVR::CPCWRdRr);
2801 EXPAND(AVR::LDIWRdK);
2802 EXPAND(AVR::LDSWRdK);
2803 EXPAND(AVR::LDWRdPtr);
2804 EXPAND(AVR::LDWRdPtrPi);
2805 EXPAND(AVR::LDWRdPtrPd);
2806 EXPAND(AVR::LDDRdPtrQ);
2807 case AVR::LDDWRdYQ: // FIXME: Remove this once PR13375 gets fixed.
2808 EXPAND(AVR::LDDWRdPtrQ);
2809 EXPAND(AVR::LPMBRdZ);
2810 EXPAND(AVR::LPMWRdZ);
2811 EXPAND(AVR::LPMWRdZPi);
2812 EXPAND(AVR::ELPMBRdZ);
2813 EXPAND(AVR::ELPMWRdZ);
2814 EXPAND(AVR::ELPMBRdZPi);
2815 EXPAND(AVR::ELPMWRdZPi);
2816 EXPAND(AVR::AtomicLoad8);
2817 EXPAND(AVR::AtomicLoad16);
2818 EXPAND(AVR::AtomicStore8);
2819 EXPAND(AVR::AtomicStore16);
2820 EXPAND(AVR::AtomicFence);
2821 EXPAND(AVR::STSWKRr);
2822 EXPAND(AVR::STWPtrRr);
2823 EXPAND(AVR::STWPtrPiRr);
2824 EXPAND(AVR::STWPtrPdRr);
2825 EXPAND(AVR::STDPtrQRr);
2826 EXPAND(AVR::STDWPtrQRr);
2827 EXPAND(AVR::STDSPQRr);
2828 EXPAND(AVR::STDWSPQRr);
2829 EXPAND(AVR::INWRdA);
2830 EXPAND(AVR::OUTWARr);
2831 EXPAND(AVR::PUSHWRr);
2832 EXPAND(AVR::POPWRd);
2833 EXPAND(AVR::ROLBRdR1);
2834 EXPAND(AVR::ROLBRdR17);
2835 EXPAND(AVR::RORBRd);
2836 EXPAND(AVR::LSLWRd);
2837 EXPAND(AVR::LSRWRd);
2838 EXPAND(AVR::RORWRd);
2839 EXPAND(AVR::ROLWRd);
2840 EXPAND(AVR::ASRWRd);
2841 EXPAND(AVR::LSLWHiRd);
2842 EXPAND(AVR::LSRWLoRd);
2843 EXPAND(AVR::ASRWLoRd);
2844 EXPAND(AVR::LSLWNRd);
2845 EXPAND(AVR::LSRWNRd);
2846 EXPAND(AVR::ASRWNRd);
2847 EXPAND(AVR::LSLBNRd);
2848 EXPAND(AVR::LSRBNRd);
2849 EXPAND(AVR::ASRBNRd);
2850 EXPAND(AVR::SEXT);
2851 EXPAND(AVR::ZEXT);
2852 EXPAND(AVR::SPREAD);
2853 EXPAND(AVR::SPWRITE);
2854 EXPAND(AVR::FRMSP);
2855 }
2856#undef EXPAND
2857 return false;
2858}
2859
2860} // end of anonymous namespace
2861
2862INITIALIZE_PASS(AVRExpandPseudoLegacy, "avr-expand-pseudo",
2863 AVR_EXPAND_PSEUDO_NAME, false, false)
2864
2865FunctionPass *llvm::createAVRExpandPseudoLegacyPass() {
2866 return new AVRExpandPseudoLegacy();
2867}
2868
2869bool AVRExpandPseudoLegacy::runOnMachineFunction(MachineFunction &MF) {
2870 AVRExpandPseudoImpl Impl;
2871 return Impl.runOnMachineFunction(MF);
2872}
2873
2874PreservedAnalyses
2875AVRExpandPseudoPass::run(MachineFunction &MF,
2876 MachineFunctionAnalysisManager &MFAM) {
2877 AVRExpandPseudoImpl Impl;
2878 return Impl.runOnMachineFunction(MF)
2879 ? getMachineFunctionPassPreservedAnalyses()
2880 .preserveSet<CFGAnalyses>()
2881 : PreservedAnalyses::all();
2882}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
Imm
uint64_t Imm
Definition AMDGPUDisassembler.cpp:552
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
EXPAND
#define EXPAND(Op)
AVR_EXPAND_PSEUDO_NAME
#define AVR_EXPAND_PSEUDO_NAME
Definition AVRExpandPseudoInsts.cpp:31
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
expand
static Expected< BitVector > expand(StringRef S, StringRef Original)
Definition GlobPattern.cpp:26
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:870
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2078
expandMBB
static bool expandMBB(MachineBasicBlock &MBB, const MipsSubtarget *STI, const MipsInstrInfo *TII)
Definition MipsExpandPseudo.cpp:1096
expandMI
static bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator &NMBB, const MipsSubtarget *STI, const MipsInstrInfo *TII)
Definition MipsExpandPseudo.cpp:1031
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
llvm::AVRExpandPseudoPass::run
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Definition AVRExpandPseudoInsts.cpp:2875
llvm::AVRMachineFunctionInfo
Contains AVR-specific information for each MachineFunction.
Definition AVRMachineFunctionInfo.h:22
llvm::AVRRegisterInfo
Utilities relating to AVR registers.
Definition AVRRegisterInfo.h:24
llvm::AVRSubtarget
A specific AVR target MCU.
Definition AVRSubtarget.h:32
llvm::AVRSubtarget::getTmpRegister
Register getTmpRegister() const
Definition AVRSubtarget.h:91
llvm::AVRSubtarget::getELFArch
unsigned getELFArch() const
Gets the ELF architecture for the e_flags field of an ELF object file.
Definition AVRSubtarget.h:74
llvm::AVRSubtarget::getFrameLowering
const TargetFrameLowering * getFrameLowering() const override
Definition AVRSubtarget.h:43
llvm::AVRSubtarget::getIORegRAMPZ
int getIORegRAMPZ() const
Get I/O register addresses.
Definition AVRSubtarget.h:81
llvm::AVRSubtarget::getIORegSPL
int getIORegSPL() const
Definition AVRSubtarget.h:83
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition AVRSubtarget.h:42
llvm::AVRSubtarget::getIORegSREG
int getIORegSREG() const
Definition AVRSubtarget.h:85
llvm::AVRSubtarget::getIORegSPH
int getIORegSPH() const
Definition AVRSubtarget.h:84
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition AVRSubtarget.h:52
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition PassAnalysisSupport.h:48
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:280
llvm::BlockAddress
The address of a basic block.
Definition Constants.h:1088
llvm::CFGAnalyses
Represents analyses that only rely on functions' control flow.
Definition Analysis.h:73
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:126
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:312
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:340
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition MachineFunctionPass.cpp:148
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:778
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition MachineFunction.h:890
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition MachineOperand.h:929
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition MachineOperand.h:53
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition MachineOperand.h:62
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition MachineOperand.h:63
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition MachineRegisterInfo.h:55
llvm::PreservedAnalyses::all
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition Analysis.h:118
llvm::PreservedAnalyses::preserveSet
PreservedAnalyses & preserveSet()
Mark an analysis set as preserved.
Definition Analysis.h:151
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::StackOffset
StackOffset holds a fixed and a scalable offset in bytes.
Definition TypeSize.h:31
llvm::StackOffset::getFixed
static StackOffset getFixed(int64_t Fixed)
Definition TypeSize.h:40
llvm::StringRef
Represent a constant reference to a string, i.e.
Definition StringRef.h:56
llvm::TargetFrameLowering::hasReservedCallFrame
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition TargetFrameLowering.h:315
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition TargetInstrInfo.h:115
Analysis.h
Pass manager infrastructure for declaring and invalidating analyses.
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AVRII::MO_HI
@ MO_HI
On a symbol operand, this represents the hi part.
Definition AVRInstrInfo.h:57
llvm::AVRII::MO_NEG
@ MO_NEG
On a symbol operand, this represents it has to be negated.
Definition AVRInstrInfo.h:60
llvm::AVRII::MO_LO
@ MO_LO
On a symbol operand, this represents the lo part.
Definition AVRInstrInfo.h:54
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:61
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition MachineInstrBuilder.h:65
llvm::RegState::Define
@ Define
Register definition.
Definition MachineInstrBuilder.h:57
llvm::getKillRegState
constexpr RegState getKillRegState(bool B)
Definition MachineInstrBuilder.h:90
llvm::createAVRExpandPseudoLegacyPass
FunctionPass * createAVRExpandPseudoLegacyPass()
llvm::MachineFunctionAnalysisManager
AnalysisManager< MachineFunction > MachineFunctionAnalysisManager
Definition MachineFunctionAnalysisManager.h:24
llvm::getDeadRegState
constexpr RegState getDeadRegState(bool B)
Definition MachineInstrBuilder.h:93
llvm::getMachineFunctionPassPreservedAnalyses
LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()
Returns the minimum set of Analyses that all machine function passes must preserve.
Definition MachinePassManager.cpp:162
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190
llvm::Op
DWARFExpression::Operation Op
Definition DWARFExpressionPrinter.cpp:25
llvm::getUndefRegState
constexpr RegState getUndefRegState(bool B)
Definition MachineInstrBuilder.h:96
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