LLVM 23.0.0git
AArch64ELFObjectWriter.cpp
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1//===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file handles ELF-specific object emission, converting LLVM's internal
10// fixups into the appropriate relocations.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/AArch64FixupKinds.h"
15#include "MCTargetDesc/AArch64MCAsmInfo.h"
16#include "MCTargetDesc/AArch64MCTargetDesc.h"
17#include "llvm/BinaryFormat/ELF.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCELFObjectWriter.h"
20#include "llvm/MC/MCFixup.h"
21#include "llvm/MC/MCObjectWriter.h"
22#include "llvm/MC/MCSymbolELF.h"
23#include "llvm/MC/MCValue.h"
24#include "llvm/Support/ErrorHandling.h"
25#include <cassert>
26#include <cstdint>
27
28using namespace llvm;
29
30namespace {
31
32class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
33public:
34 AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
35
36 ~AArch64ELFObjectWriter() override = default;
37
38protected:
39 unsigned getRelocType(const MCFixup &, const MCValue &,
40 bool IsPCRel) const override;
41 bool needsRelocateWithSymbol(const MCValue &, unsigned Type) const override;
42 bool isNonILP32reloc(const MCFixup &Fixup, AArch64::Specifier RefKind) const;
43 void sortRelocs(std::vector<ELFRelocationEntry> &Relocs) override;
44
45 bool IsILP32;
46};
47
48} // end anonymous namespace
49
50AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
51 : MCELFObjectTargetWriter(/*Is64Bit*/ !IsILP32, OSABI, ELF::EM_AARCH64,
52 /*HasRelocationAddend*/ true),
53 IsILP32(IsILP32) {}
54
55#define R_CLS(rtype) \
56 IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
57
58// assumes IsILP32 is true
59bool AArch64ELFObjectWriter::isNonILP32reloc(const MCFixup &Fixup,
60 AArch64::Specifier RefKind) const {
61 if (Fixup.getKind() != AArch64::fixup_aarch64_movw)
62 return false;
63 switch (RefKind) {
64 case AArch64::S_ABS_G3:
65 case AArch64::S_ABS_G2:
66 case AArch64::S_ABS_G2_S:
67 case AArch64::S_ABS_G2_NC:
68 case AArch64::S_ABS_G1_S:
69 case AArch64::S_ABS_G1_NC:
70 case AArch64::S_DTPREL_G2:
71 case AArch64::S_DTPREL_G1_NC:
72 case AArch64::S_TPREL_G2:
73 case AArch64::S_TPREL_G1_NC:
74 case AArch64::S_GOTTPREL_G1:
75 case AArch64::S_GOTTPREL_G0_NC:
76 reportError(Fixup.getLoc(),
77 "absolute MOV relocation is not supported in ILP32");
78 return true;
79 default:
80 return false;
81 }
82 return false;
83}
84
85unsigned AArch64ELFObjectWriter::getRelocType(const MCFixup &Fixup,
86 const MCValue &Target,
87 bool IsPCRel) const {
88 auto Kind = Fixup.getKind();
89 AArch64::Specifier RefKind =
90 static_cast<AArch64::Specifier>(Target.getSpecifier());
91 AArch64::Specifier SymLoc = AArch64::getSymbolLoc(RefKind);
92 bool IsNC = AArch64::isNotChecked(RefKind);
93
94 switch (SymLoc) {
95 case AArch64::S_DTPREL:
96 case AArch64::S_GOTTPREL:
97 case AArch64::S_TPREL:
98 case AArch64::S_TLSDESC:
99 case AArch64::S_TLSDESC_AUTH:
100 if (auto *SA = const_cast<MCSymbol *>(Target.getAddSym()))
101 static_cast<MCSymbolELF *>(SA)->setType(ELF::STT_TLS);
102 break;
103 default:
104 break;
105 }
106
107 switch (RefKind) {
108 case AArch64::S_GOTPCREL:
109 case AArch64::S_PLT:
110 if (Kind == FK_Data_4)
111 break;
112 // Only R_AARCH64_PLT32/R_AARCH64_GOTPCREL32 defined at present, but can
113 // be extended to other sizes if additional relocations are defined.
114 reportError(Fixup.getLoc(), AArch64::getSpecifierName(RefKind) +
115 " can only be used in a .word directive");
116 return ELF::R_AARCH64_NONE;
117 default:
118 break;
119 }
120
121 // Extract the relocation type from the fixup kind, after applying STT_TLS as
122 // needed.
123 if (mc::isRelocation(Fixup.getKind()))
124 return Kind;
125
126 if (IsPCRel) {
127 switch (Kind) {
128 case FK_Data_1:
129 reportError(Fixup.getLoc(), "1-byte data relocations not supported");
130 return ELF::R_AARCH64_NONE;
131 case FK_Data_2:
132 return R_CLS(PREL16);
133 case FK_Data_4: {
134 return R_CLS(PREL32);
135 }
136 case FK_Data_8:
137 if (IsILP32) {
138 reportError(Fixup.getLoc(), "8 byte PC relative data "
139 "relocation is not supported in ILP32");
140 return ELF::R_AARCH64_NONE;
141 }
142 return ELF::R_AARCH64_PREL64;
143 case AArch64::fixup_aarch64_pcrel_adr_imm21:
144 if (SymLoc == AArch64::S_GOT_AUTH) {
145 if (IsILP32) {
146 reportError(Fixup.getLoc(),
147 "ADR AUTH relocation is not supported in ILP32");
148 return ELF::R_AARCH64_NONE;
149 }
150 return ELF::R_AARCH64_AUTH_GOT_ADR_PREL_LO21;
151 }
152 if (SymLoc != AArch64::S_ABS)
153 reportError(Fixup.getLoc(), "invalid symbol kind for ADR relocation");
154 return R_CLS(ADR_PREL_LO21);
155 case AArch64::fixup_aarch64_pcrel_adrp_imm21:
156 if (SymLoc == AArch64::S_ABS && !IsNC)
157 return R_CLS(ADR_PREL_PG_HI21);
158 if (SymLoc == AArch64::S_ABS && IsNC) {
159 if (IsILP32) {
160 reportError(Fixup.getLoc(),
161 "invalid fixup for 32-bit pcrel ADRP instruction "
162 "VK_ABS VK_NC");
163 return ELF::R_AARCH64_NONE;
164 }
165 return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
166 }
167 if (SymLoc == AArch64::S_GOT && !IsNC)
168 return R_CLS(ADR_GOT_PAGE);
169 if (SymLoc == AArch64::S_GOT_AUTH && !IsNC) {
170 if (IsILP32) {
171 reportError(Fixup.getLoc(),
172 "ADRP AUTH relocation is not supported in ILP32");
173 return ELF::R_AARCH64_NONE;
174 }
175 return ELF::R_AARCH64_AUTH_ADR_GOT_PAGE;
176 }
177 if (SymLoc == AArch64::S_GOTTPREL && !IsNC)
178 return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
179 if (SymLoc == AArch64::S_TLSDESC && !IsNC)
180 return R_CLS(TLSDESC_ADR_PAGE21);
181 if (SymLoc == AArch64::S_TLSDESC_AUTH && !IsNC) {
182 if (IsILP32) {
183 reportError(Fixup.getLoc(),
184 "ADRP AUTH relocation is not supported in ILP32");
185 return ELF::R_AARCH64_NONE;
186 }
187 return ELF::R_AARCH64_AUTH_TLSDESC_ADR_PAGE21;
188 }
189 reportError(Fixup.getLoc(), "invalid symbol kind for ADRP relocation");
190 return ELF::R_AARCH64_NONE;
191 case AArch64::fixup_aarch64_pcrel_branch26:
192 return R_CLS(JUMP26);
193 case AArch64::fixup_aarch64_pcrel_call26:
194 return R_CLS(CALL26);
195 case AArch64::fixup_aarch64_ldr_pcrel_imm19:
196 if (SymLoc == AArch64::S_GOTTPREL)
197 return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
198 if (SymLoc == AArch64::S_GOT)
199 return R_CLS(GOT_LD_PREL19);
200 if (SymLoc == AArch64::S_GOT_AUTH) {
201 if (IsILP32) {
202 reportError(Fixup.getLoc(),
203 "LDR AUTH relocation is not supported in ILP32");
204 return ELF::R_AARCH64_NONE;
205 }
206 return ELF::R_AARCH64_AUTH_GOT_LD_PREL19;
207 }
208 return R_CLS(LD_PREL_LO19);
209 case AArch64::fixup_aarch64_pcrel_branch14:
210 return R_CLS(TSTBR14);
211 case AArch64::fixup_aarch64_pcrel_branch16:
212 reportError(Fixup.getLoc(),
213 "relocation of PAC/AUT instructions is not supported");
214 return ELF::R_AARCH64_NONE;
215 case AArch64::fixup_aarch64_pcrel_branch9:
216 reportError(
217 Fixup.getLoc(),
218 "relocation of compare-and-branch instructions not supported");
219 return ELF::R_AARCH64_NONE;
220 case AArch64::fixup_aarch64_pcrel_branch19:
221 return R_CLS(CONDBR19);
222 default:
223 reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
224 return ELF::R_AARCH64_NONE;
225 }
226 } else {
227 if (IsILP32 && isNonILP32reloc(Fixup, RefKind))
228 return ELF::R_AARCH64_NONE;
229 switch (Fixup.getKind()) {
230 case FK_Data_1:
231 reportError(Fixup.getLoc(), "1-byte data relocations not supported");
232 return ELF::R_AARCH64_NONE;
233 case FK_Data_2:
234 return R_CLS(ABS16);
235 case FK_Data_4:
236 if (!IsILP32) {
237 if (Target.getSpecifier() == AArch64::S_GOTPCREL)
238 return ELF::R_AARCH64_GOTPCREL32;
239 if (Target.getSpecifier() == AArch64::S_PLT)
240 return ELF::R_AARCH64_PLT32;
241 }
242 return R_CLS(ABS32);
243 case FK_Data_8: {
244 if (IsILP32) {
245 reportError(
246 Fixup.getLoc(),
247 "8 byte absolute data relocation is not supported in ILP32");
248 return ELF::R_AARCH64_NONE;
249 }
250 if (RefKind == AArch64::S_AUTH || RefKind == AArch64::S_AUTHADDR)
251 return ELF::R_AARCH64_AUTH_ABS64;
252 if (RefKind == AArch64::S_FUNCINIT)
253 return ELF::R_AARCH64_FUNCINIT64;
254 return ELF::R_AARCH64_ABS64;
255 }
256 case AArch64::fixup_aarch64_add_imm12:
257 if (RefKind == AArch64::S_DTPREL_HI12)
258 return R_CLS(TLSLD_ADD_DTPREL_HI12);
259 if (RefKind == AArch64::S_TPREL_HI12)
260 return R_CLS(TLSLE_ADD_TPREL_HI12);
261 if (RefKind == AArch64::S_DTPREL_LO12_NC)
262 return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
263 if (RefKind == AArch64::S_DTPREL_LO12)
264 return R_CLS(TLSLD_ADD_DTPREL_LO12);
265 if (RefKind == AArch64::S_TPREL_LO12_NC)
266 return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
267 if (RefKind == AArch64::S_TPREL_LO12)
268 return R_CLS(TLSLE_ADD_TPREL_LO12);
269 if (RefKind == AArch64::S_TLSDESC_LO12)
270 return R_CLS(TLSDESC_ADD_LO12);
271 if (RefKind == AArch64::S_TLSDESC_AUTH_LO12) {
272 if (IsILP32) {
273 reportError(Fixup.getLoc(),
274 "ADD AUTH relocation is not supported in ILP32");
275 return ELF::R_AARCH64_NONE;
276 }
277 return ELF::R_AARCH64_AUTH_TLSDESC_ADD_LO12;
278 }
279 if (RefKind == AArch64::S_GOT_AUTH_LO12 && IsNC) {
280 if (IsILP32) {
281 reportError(Fixup.getLoc(),
282 "ADD AUTH relocation is not supported in ILP32");
283 return ELF::R_AARCH64_NONE;
284 }
285 return ELF::R_AARCH64_AUTH_GOT_ADD_LO12_NC;
286 }
287 if (SymLoc == AArch64::S_ABS && IsNC)
288 return R_CLS(ADD_ABS_LO12_NC);
289
290 reportError(Fixup.getLoc(), "invalid fixup for add (uimm12) instruction");
291 return ELF::R_AARCH64_NONE;
292 case AArch64::fixup_aarch64_ldst_imm12_scale1:
293 if (SymLoc == AArch64::S_ABS && IsNC)
294 return R_CLS(LDST8_ABS_LO12_NC);
295 if (SymLoc == AArch64::S_DTPREL && !IsNC)
296 return R_CLS(TLSLD_LDST8_DTPREL_LO12);
297 if (SymLoc == AArch64::S_DTPREL && IsNC)
298 return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
299 if (SymLoc == AArch64::S_TPREL && !IsNC)
300 return R_CLS(TLSLE_LDST8_TPREL_LO12);
301 if (SymLoc == AArch64::S_TPREL && IsNC)
302 return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
303
304 reportError(Fixup.getLoc(),
305 "invalid fixup for 8-bit load/store instruction");
306 return ELF::R_AARCH64_NONE;
307 case AArch64::fixup_aarch64_ldst_imm12_scale2:
308 if (SymLoc == AArch64::S_ABS && IsNC)
309 return R_CLS(LDST16_ABS_LO12_NC);
310 if (SymLoc == AArch64::S_DTPREL && !IsNC)
311 return R_CLS(TLSLD_LDST16_DTPREL_LO12);
312 if (SymLoc == AArch64::S_DTPREL && IsNC)
313 return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
314 if (SymLoc == AArch64::S_TPREL && !IsNC)
315 return R_CLS(TLSLE_LDST16_TPREL_LO12);
316 if (SymLoc == AArch64::S_TPREL && IsNC)
317 return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
318
319 reportError(Fixup.getLoc(),
320 "invalid fixup for 16-bit load/store instruction");
321 return ELF::R_AARCH64_NONE;
322 case AArch64::fixup_aarch64_ldst_imm12_scale4:
323 if (SymLoc == AArch64::S_ABS && IsNC)
324 return R_CLS(LDST32_ABS_LO12_NC);
325 if (SymLoc == AArch64::S_DTPREL && !IsNC)
326 return R_CLS(TLSLD_LDST32_DTPREL_LO12);
327 if (SymLoc == AArch64::S_DTPREL && IsNC)
328 return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
329 if (SymLoc == AArch64::S_TPREL && !IsNC)
330 return R_CLS(TLSLE_LDST32_TPREL_LO12);
331 if (SymLoc == AArch64::S_TPREL && IsNC)
332 return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
333 if (SymLoc == AArch64::S_GOT && IsNC) {
334 if (IsILP32)
335 return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
336 reportError(Fixup.getLoc(), "4 byte unchecked GOT load/store "
337 "relocation is not supported in LP64");
338 return ELF::R_AARCH64_NONE;
339 }
340 if (SymLoc == AArch64::S_GOT && !IsNC) {
341 if (IsILP32) {
342 reportError(
343 Fixup.getLoc(),
344 "4 byte checked GOT load/store relocation is not supported");
345 }
346 return ELF::R_AARCH64_NONE;
347 }
348 if (SymLoc == AArch64::S_GOTTPREL && IsNC) {
349 if (IsILP32)
350 return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
351 reportError(Fixup.getLoc(), "32-bit load/store "
352 "relocation is not supported in LP64");
353 return ELF::R_AARCH64_NONE;
354 }
355 if (SymLoc == AArch64::S_TLSDESC && !IsNC) {
356 if (IsILP32)
357 return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
358 reportError(
359 Fixup.getLoc(),
360 "4 byte TLSDESC load/store relocation is not supported in LP64");
361 return ELF::R_AARCH64_NONE;
362 }
363
364 reportError(Fixup.getLoc(),
365 "invalid fixup for 32-bit load/store instruction "
366 "fixup_aarch64_ldst_imm12_scale4");
367 return ELF::R_AARCH64_NONE;
368 case AArch64::fixup_aarch64_ldst_imm12_scale8:
369 if (SymLoc == AArch64::S_ABS && IsNC)
370 return R_CLS(LDST64_ABS_LO12_NC);
371 if ((SymLoc == AArch64::S_GOT || SymLoc == AArch64::S_GOT_AUTH) && IsNC) {
372 AArch64::Specifier AddressLoc = AArch64::getAddressFrag(RefKind);
373 bool IsAuth = (SymLoc == AArch64::S_GOT_AUTH);
374 if (!IsILP32) {
375 if (AddressLoc == AArch64::S_LO15)
376 return ELF::R_AARCH64_LD64_GOTPAGE_LO15;
377 return (IsAuth ? ELF::R_AARCH64_AUTH_LD64_GOT_LO12_NC
378 : ELF::R_AARCH64_LD64_GOT_LO12_NC);
379 }
380 reportError(Fixup.getLoc(),
381 "64-bit load/store relocation is not supported in ILP32");
382 return ELF::R_AARCH64_NONE;
383 }
384 if (SymLoc == AArch64::S_DTPREL && !IsNC)
385 return R_CLS(TLSLD_LDST64_DTPREL_LO12);
386 if (SymLoc == AArch64::S_DTPREL && IsNC)
387 return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
388 if (SymLoc == AArch64::S_TPREL && !IsNC)
389 return R_CLS(TLSLE_LDST64_TPREL_LO12);
390 if (SymLoc == AArch64::S_TPREL && IsNC)
391 return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
392 if (SymLoc == AArch64::S_GOTTPREL && IsNC) {
393 if (!IsILP32)
394 return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
395 reportError(Fixup.getLoc(),
396 "64-bit load/store relocation is not supported in ILP32");
397 return ELF::R_AARCH64_NONE;
398 }
399 if (SymLoc == AArch64::S_TLSDESC) {
400 if (!IsILP32)
401 return ELF::R_AARCH64_TLSDESC_LD64_LO12;
402 reportError(Fixup.getLoc(),
403 "64-bit load/store relocation is not supported in ILP32");
404 return ELF::R_AARCH64_NONE;
405 }
406 if (SymLoc == AArch64::S_TLSDESC_AUTH) {
407 if (!IsILP32)
408 return ELF::R_AARCH64_AUTH_TLSDESC_LD64_LO12;
409 reportError(
410 Fixup.getLoc(),
411 "64-bit load/store AUTH relocation is not supported in ILP32");
412 return ELF::R_AARCH64_NONE;
413 }
414 reportError(Fixup.getLoc(),
415 "invalid fixup for 64-bit load/store instruction");
416 return ELF::R_AARCH64_NONE;
417 case AArch64::fixup_aarch64_ldst_imm12_scale16:
418 if (SymLoc == AArch64::S_ABS && IsNC)
419 return R_CLS(LDST128_ABS_LO12_NC);
420 if (SymLoc == AArch64::S_DTPREL && !IsNC)
421 return R_CLS(TLSLD_LDST128_DTPREL_LO12);
422 if (SymLoc == AArch64::S_DTPREL && IsNC)
423 return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
424 if (SymLoc == AArch64::S_TPREL && !IsNC)
425 return R_CLS(TLSLE_LDST128_TPREL_LO12);
426 if (SymLoc == AArch64::S_TPREL && IsNC)
427 return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
428
429 reportError(Fixup.getLoc(),
430 "invalid fixup for 128-bit load/store instruction");
431 return ELF::R_AARCH64_NONE;
432 // ILP32 case not reached here, tested with isNonILP32reloc
433 case AArch64::fixup_aarch64_movw:
434 if (RefKind == AArch64::S_ABS_G3)
435 return ELF::R_AARCH64_MOVW_UABS_G3;
436 if (RefKind == AArch64::S_ABS_G2)
437 return ELF::R_AARCH64_MOVW_UABS_G2;
438 if (RefKind == AArch64::S_ABS_G2_S)
439 return ELF::R_AARCH64_MOVW_SABS_G2;
440 if (RefKind == AArch64::S_ABS_G2_NC)
441 return ELF::R_AARCH64_MOVW_UABS_G2_NC;
442 if (RefKind == AArch64::S_ABS_G1)
443 return R_CLS(MOVW_UABS_G1);
444 if (RefKind == AArch64::S_ABS_G1_S)
445 return ELF::R_AARCH64_MOVW_SABS_G1;
446 if (RefKind == AArch64::S_ABS_G1_NC)
447 return ELF::R_AARCH64_MOVW_UABS_G1_NC;
448 if (RefKind == AArch64::S_ABS_G0)
449 return R_CLS(MOVW_UABS_G0);
450 if (RefKind == AArch64::S_ABS_G0_S)
451 return R_CLS(MOVW_SABS_G0);
452 if (RefKind == AArch64::S_ABS_G0_NC)
453 return R_CLS(MOVW_UABS_G0_NC);
454 if (RefKind == AArch64::S_PREL_G3)
455 return ELF::R_AARCH64_MOVW_PREL_G3;
456 if (RefKind == AArch64::S_PREL_G2)
457 return ELF::R_AARCH64_MOVW_PREL_G2;
458 if (RefKind == AArch64::S_PREL_G2_NC)
459 return ELF::R_AARCH64_MOVW_PREL_G2_NC;
460 if (RefKind == AArch64::S_PREL_G1)
461 return R_CLS(MOVW_PREL_G1);
462 if (RefKind == AArch64::S_PREL_G1_NC)
463 return ELF::R_AARCH64_MOVW_PREL_G1_NC;
464 if (RefKind == AArch64::S_PREL_G0)
465 return R_CLS(MOVW_PREL_G0);
466 if (RefKind == AArch64::S_PREL_G0_NC)
467 return R_CLS(MOVW_PREL_G0_NC);
468 if (RefKind == AArch64::S_DTPREL_G2)
469 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
470 if (RefKind == AArch64::S_DTPREL_G1)
471 return R_CLS(TLSLD_MOVW_DTPREL_G1);
472 if (RefKind == AArch64::S_DTPREL_G1_NC)
473 return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
474 if (RefKind == AArch64::S_DTPREL_G0)
475 return R_CLS(TLSLD_MOVW_DTPREL_G0);
476 if (RefKind == AArch64::S_DTPREL_G0_NC)
477 return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
478 if (RefKind == AArch64::S_TPREL_G2)
479 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
480 if (RefKind == AArch64::S_TPREL_G1)
481 return R_CLS(TLSLE_MOVW_TPREL_G1);
482 if (RefKind == AArch64::S_TPREL_G1_NC)
483 return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
484 if (RefKind == AArch64::S_TPREL_G0)
485 return R_CLS(TLSLE_MOVW_TPREL_G0);
486 if (RefKind == AArch64::S_TPREL_G0_NC)
487 return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
488 if (RefKind == AArch64::S_GOTTPREL_G1)
489 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
490 if (RefKind == AArch64::S_GOTTPREL_G0_NC)
491 return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
492 reportError(Fixup.getLoc(), "invalid fixup for movz/movk instruction");
493 return ELF::R_AARCH64_NONE;
494 default:
495 reportError(Fixup.getLoc(), "Unknown ELF relocation type");
496 return ELF::R_AARCH64_NONE;
497 }
498 }
499
500 llvm_unreachable("Unimplemented fixup -> relocation");
501}
502
503bool AArch64ELFObjectWriter::needsRelocateWithSymbol(const MCValue &Val,
504 unsigned) const {
505 // For memory-tagged symbols, ensure that the relocation uses the symbol. For
506 // tagged symbols, we emit an empty relocation (R_AARCH64_NONE) in a special
507 // section (SHT_AARCH64_MEMTAG_GLOBALS_STATIC) to indicate to the linker that
508 // this global needs to be tagged. In addition, the linker needs to know
509 // whether to emit a special addend when relocating `end` symbols, and this
510 // can only be determined by the attributes of the symbol itself.
511 if (Val.getAddSym() &&
512 static_cast<const MCSymbolELF *>(Val.getAddSym())->isMemtag())
513 return true;
514
515 if ((Val.getSpecifier() & AArch64::S_GOT) == AArch64::S_GOT)
516 return true;
517 return is_contained({AArch64::S_GOTPCREL, AArch64::S_PLT},
518 Val.getSpecifier());
519}
520
521void AArch64ELFObjectWriter::sortRelocs(
522 std::vector<ELFRelocationEntry> &Relocs) {
523 // PATCHINST relocations should be applied last because they may overwrite the
524 // whole instruction and so should take precedence over other relocations that
525 // modify operands of the original instruction.
526 std::stable_partition(Relocs.begin(), Relocs.end(),
527 [](const ELFRelocationEntry &R) {
528 return R.Type != ELF::R_AARCH64_PATCHINST;
529 });
530}
531
532std::unique_ptr<MCObjectTargetWriter>
533llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) {
534 return std::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
535}
R_CLS
#define R_CLS(rtype)
Definition AArch64ELFObjectWriter.cpp:55
reportError
static Error reportError(StringRef Message)
Definition BitcodeAnalyzer.cpp:20
Fixup
PowerPC TLS Dynamic Call Fixup
Definition PPCTLSDynamicCall.cpp:337
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition MCFixup.h:61
llvm::MCValue::getAddSym
const MCSymbol * getAddSym() const
Definition MCValue.h:49
llvm::MCValue::getSpecifier
uint32_t getSpecifier() const
Definition MCValue.h:46
uint8_t
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::AArch64::getSymbolLoc
Specifier getSymbolLoc(Specifier S)
Definition AArch64MCAsmInfo.h:189
llvm::AArch64::getSpecifierName
StringRef getSpecifierName(Specifier S)
Return the string representation of the ELF relocation specifier (e.g.
Definition AArch64MCAsmInfo.cpp:54
llvm::AArch64::isNotChecked
bool isNotChecked(Specifier S)
Definition AArch64MCAsmInfo.h:197
llvm::AArch64::getAddressFrag
Specifier getAddressFrag(Specifier S)
Definition AArch64MCAsmInfo.h:193
llvm::ELF::EM_AARCH64
@ EM_AARCH64
Definition ELF.h:285
llvm::ELF::STT_TLS
@ STT_TLS
Definition ELF.h:1424
llvm::mc::isRelocation
bool isRelocation(MCFixupKind FixupKind)
Definition MCFixup.h:130
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition Types.h:26
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition MCFixup.h:37
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition MCFixup.h:34
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition MCFixup.h:36
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition MCFixup.h:35
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition STLExtras.h:1947
llvm::createAArch64ELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
Definition AArch64ELFObjectWriter.cpp:533
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