Syntax of GFX12 Instructions¶
Introduction¶
This document describes the syntax of GFX12 instructions.
Notation¶
Notation used in this document is explained here.
Overview¶
An overview of generic syntax and other features of AMDGPU instructions may be found in this document.
Instructions¶
SMEM¶
INSTRUCTION DST SRC0 SRC1 SRC2 SRC3 MODIFIERS —————————————————————————————————————————————————————————————————————————————————————————————————— s_atc_probe sdata, sbase, soffset offset24s th scope nv s_atc_probe_buffer sdata, sbase, soffset offset24s th scope nv s_buffer_load_b128 sdata, sbase, soffset offset24s th scope nv s_buffer_load_b256 sdata, sbase, soffset offset24s th scope nv s_buffer_load_b32 sdata, sbase, soffset offset24s th scope nv s_buffer_load_b512 sdata, sbase, soffset offset24s th scope nv s_buffer_load_b64 sdata, sbase, soffset offset24s th scope nv s_buffer_load_b96 sdata, sbase, soffset offset24s th scope nv s_buffer_load_i16 sdata, sbase, soffset offset24s th scope nv s_buffer_load_i8 sdata, sbase, soffset offset24s th scope nv s_buffer_load_u16 sdata, sbase, soffset offset24s th scope nv s_buffer_load_u8 sdata, sbase, soffset offset24s th scope nv s_buffer_prefetch_data sbase, ioffset, soffset, sdata offset24s th scope nv s_dcache_inv offset24s th scope nv s_load_b128 sdata, sbase, soffset offset24s th scope nv s_load_b256 sdata, sbase, soffset offset24s th scope nv s_load_b32 sdata, sbase, soffset offset24s th scope nv s_load_b512 sdata, sbase, soffset offset24s th scope nv s_load_b64 sdata, sbase, soffset offset24s th scope nv s_load_b96 sdata, sbase, soffset offset24s th scope nv s_load_i16 sdata, sbase, soffset offset24s th scope nv s_load_i8 sdata, sbase, soffset offset24s th scope nv s_load_u16 sdata, sbase, soffset offset24s th scope nv s_load_u8 sdata, sbase, soffset offset24s th scope nv s_prefetch_data sbase, ioffset, soffset, sdata offset24s th scope nv s_prefetch_data_pc_rel ioffset, soffset, sdata offset24s th scope nv s_prefetch_inst sbase, ioffset, soffset, sdata offset24s th scope nv s_prefetch_inst_pc_rel ioffset, soffset, sdata offset24s th scope nv
SOP1¶
INSTRUCTION DST SRC ——————————————————————————————————————————————————— s_abs_i32 sdst, ssrc0 s_alloc_vgpr ssrc0 s_and_not0_saveexec_b32 sdst, ssrc0 s_and_not0_saveexec_b64 sdst, ssrc0 s_and_not0_wrexec_b32 sdst, ssrc0 s_and_not0_wrexec_b64 sdst, ssrc0 s_and_not1_saveexec_b32 sdst, ssrc0 s_and_not1_saveexec_b64 sdst, ssrc0 s_and_not1_wrexec_b32 sdst, ssrc0 s_and_not1_wrexec_b64 sdst, ssrc0 s_and_saveexec_b32 sdst, ssrc0 s_and_saveexec_b64 sdst, ssrc0 s_barrier_signal ssrc0 s_barrier_signal_isfirst ssrc0 s_bcnt0_i32_b32 sdst, ssrc0 s_bcnt0_i32_b64 sdst, ssrc0 s_bcnt1_i32_b32 sdst, ssrc0 s_bcnt1_i32_b64 sdst, ssrc0 s_bitreplicate_b64_b32 sdst, ssrc0 s_bitset0_b32 sdst, ssrc0 s_bitset0_b64 sdst, ssrc0 s_bitset1_b32 sdst, ssrc0 s_bitset1_b64 sdst, ssrc0 s_brev_b32 sdst, ssrc0 s_brev_b64 sdst, ssrc0 s_ceil_f16 sdst, ssrc0 s_ceil_f32 sdst, ssrc0 s_cls_i32 sdst, ssrc0 s_cls_i32_i64 sdst, ssrc0 s_clz_i32_u32 sdst, ssrc0 s_clz_i32_u64 sdst, ssrc0 s_cmov_b32 sdst, ssrc0 s_cmov_b64 sdst, ssrc0 s_ctz_i32_b32 sdst, ssrc0 s_ctz_i32_b64 sdst, ssrc0 s_cvt_f16_f32 sdst, ssrc0 s_cvt_f32_f16 sdst, ssrc0 s_cvt_f32_i32 sdst, ssrc0 s_cvt_f32_u32 sdst, ssrc0 s_cvt_hi_f32_f16 sdst, ssrc0 s_cvt_i32_f32 sdst, ssrc0 s_cvt_u32_f32 sdst, ssrc0 s_floor_f16 sdst, ssrc0 s_floor_f32 sdst, ssrc0 s_getpc_b64 sdst s_mov_b32 sdst, ssrc0 s_mov_b64 sdst, ssrc0 s_movreld_b32 sdst, ssrc0 s_movreld_b64 sdst, ssrc0 s_movrels_b32 sdst, ssrc0 s_movrels_b64 sdst, ssrc0 s_movrelsd_2_b32 sdst, ssrc0 s_nand_saveexec_b32 sdst, ssrc0 s_nand_saveexec_b64 sdst, ssrc0 s_nor_saveexec_b32 sdst, ssrc0 s_nor_saveexec_b64 sdst, ssrc0 s_not_b32 sdst, ssrc0 s_not_b64 sdst, ssrc0 s_or_not0_saveexec_b32 sdst, ssrc0 s_or_not0_saveexec_b64 sdst, ssrc0 s_or_not1_saveexec_b32 sdst, ssrc0 s_or_not1_saveexec_b64 sdst, ssrc0 s_or_saveexec_b32 sdst, ssrc0 s_or_saveexec_b64 sdst, ssrc0 s_quadmask_b32 sdst, ssrc0 s_quadmask_b64 sdst, ssrc0 s_rfe_b64 ssrc0 s_rndne_f16 sdst, ssrc0 s_rndne_f32 sdst, ssrc0 s_sendmsg_rtn_b32 sdst, ssrc0 s_sendmsg_rtn_b64 sdst, ssrc0 s_setpc_b64 ssrc0 s_sext_i32_i16 sdst, ssrc0 s_sext_i32_i8 sdst, ssrc0 s_sleep_var ssrc0 s_swappc_b64 sdst, ssrc0 s_trunc_f16 sdst, ssrc0 s_trunc_f32 sdst, ssrc0 s_wqm_b32 sdst, ssrc0 s_wqm_b64 sdst, ssrc0 s_xnor_saveexec_b32 sdst, ssrc0 s_xnor_saveexec_b64 sdst, ssrc0 s_xor_saveexec_b32 sdst, ssrc0 s_xor_saveexec_b64 sdst, ssrc0
SOP2¶
INSTRUCTION DST SRC0 SRC1 SRC2 ——————————————————————————————————————————————————————————————————————— s_absdiff_i32 sdst, ssrc0, ssrc1 s_add_co_ci_u32 sdst, ssrc0, ssrc1 s_add_co_i32 sdst, ssrc0, ssrc1 s_add_co_u32 sdst, ssrc0, ssrc1 s_add_f16 sdst, ssrc0, ssrc1 s_add_f32 sdst, ssrc0, ssrc1 s_add_nc_u64 sdst, ssrc0, ssrc1 s_and_b32 sdst, ssrc0, ssrc1 s_and_b64 sdst, ssrc0, ssrc1 s_and_not1_b32 sdst, ssrc0, ssrc1 s_and_not1_b64 sdst, ssrc0, ssrc1 s_ashr_i32 sdst, ssrc0, ssrc1 s_ashr_i64 sdst, ssrc0, ssrc1 s_bfe_i32 sdst, ssrc0, ssrc1 s_bfe_i64 sdst, ssrc0, ssrc1 s_bfe_u32 sdst, ssrc0, ssrc1 s_bfe_u64 sdst, ssrc0, ssrc1 s_bfm_b32 sdst, ssrc0, ssrc1 s_bfm_b64 sdst, ssrc0, ssrc1 s_cselect_b32 sdst, ssrc0, ssrc1 s_cselect_b64 sdst, ssrc0, ssrc1 s_cvt_pk_rtz_f16_f32 sdst, ssrc0, ssrc1 s_fmaak_f32 sdst, ssrc0, ssrc1, literal s_fmac_f16 sdst, ssrc0, ssrc1 s_fmac_f32 sdst, ssrc0, ssrc1 s_fmamk_f32 sdst, ssrc0, literal, ssrc1 s_lshl1_add_u32 sdst, ssrc0, ssrc1 s_lshl2_add_u32 sdst, ssrc0, ssrc1 s_lshl3_add_u32 sdst, ssrc0, ssrc1 s_lshl4_add_u32 sdst, ssrc0, ssrc1 s_lshl_b32 sdst, ssrc0, ssrc1 s_lshl_b64 sdst, ssrc0, ssrc1 s_lshr_b32 sdst, ssrc0, ssrc1 s_lshr_b64 sdst, ssrc0, ssrc1 s_max_i32 sdst, ssrc0, ssrc1 s_max_num_f16 sdst, ssrc0, ssrc1 s_max_num_f32 sdst, ssrc0, ssrc1 s_max_u32 sdst, ssrc0, ssrc1 s_maximum_f16 sdst, ssrc0, ssrc1 s_maximum_f32 sdst, ssrc0, ssrc1 s_min_i32 sdst, ssrc0, ssrc1 s_min_num_f16 sdst, ssrc0, ssrc1 s_min_num_f32 sdst, ssrc0, ssrc1 s_min_u32 sdst, ssrc0, ssrc1 s_minimum_f16 sdst, ssrc0, ssrc1 s_minimum_f32 sdst, ssrc0, ssrc1 s_mul_f16 sdst, ssrc0, ssrc1 s_mul_f32 sdst, ssrc0, ssrc1 s_mul_hi_i32 sdst, ssrc0, ssrc1 s_mul_hi_u32 sdst, ssrc0, ssrc1 s_mul_i32 sdst, ssrc0, ssrc1 s_mul_u64 sdst, ssrc0, ssrc1 s_nand_b32 sdst, ssrc0, ssrc1 s_nand_b64 sdst, ssrc0, ssrc1 s_nor_b32 sdst, ssrc0, ssrc1 s_nor_b64 sdst, ssrc0, ssrc1 s_or_b32 sdst, ssrc0, ssrc1 s_or_b64 sdst, ssrc0, ssrc1 s_or_not1_b32 sdst, ssrc0, ssrc1 s_or_not1_b64 sdst, ssrc0, ssrc1 s_pack_hh_b32_b16 sdst, ssrc0, ssrc1 s_pack_hl_b32_b16 sdst, ssrc0, ssrc1 s_pack_lh_b32_b16 sdst, ssrc0, ssrc1 s_pack_ll_b32_b16 sdst, ssrc0, ssrc1 s_sub_co_ci_u32 sdst, ssrc0, ssrc1 s_sub_co_i32 sdst, ssrc0, ssrc1 s_sub_co_u32 sdst, ssrc0, ssrc1 s_sub_f16 sdst, ssrc0, ssrc1 s_sub_f32 sdst, ssrc0, ssrc1 s_sub_nc_u64 sdst, ssrc0, ssrc1 s_xnor_b32 sdst, ssrc0, ssrc1 s_xnor_b64 sdst, ssrc0, ssrc1 s_xor_b32 sdst, ssrc0, ssrc1 s_xor_b64 sdst, ssrc0, ssrc1
SOPC¶
INSTRUCTION SRC0 SRC1 ——————————————————————————————————————————————————— s_bitcmp0_b32 ssrc0, ssrc1 s_bitcmp0_b64 ssrc0, ssrc1 s_bitcmp1_b32 ssrc0, ssrc1 s_bitcmp1_b64 ssrc0, ssrc1 s_cmp_eq_f16 ssrc0, ssrc1 s_cmp_eq_f32 ssrc0, ssrc1 s_cmp_eq_i32 ssrc0, ssrc1 s_cmp_eq_u32 ssrc0, ssrc1 s_cmp_eq_u64 ssrc0, ssrc1 s_cmp_ge_f16 ssrc0, ssrc1 s_cmp_ge_f32 ssrc0, ssrc1 s_cmp_ge_i32 ssrc0, ssrc1 s_cmp_ge_u32 ssrc0, ssrc1 s_cmp_gt_f16 ssrc0, ssrc1 s_cmp_gt_f32 ssrc0, ssrc1 s_cmp_gt_i32 ssrc0, ssrc1 s_cmp_gt_u32 ssrc0, ssrc1 s_cmp_le_f16 ssrc0, ssrc1 s_cmp_le_f32 ssrc0, ssrc1 s_cmp_le_i32 ssrc0, ssrc1 s_cmp_le_u32 ssrc0, ssrc1 s_cmp_lg_f16 ssrc0, ssrc1 s_cmp_lg_f32 ssrc0, ssrc1 s_cmp_lg_i32 ssrc0, ssrc1 s_cmp_lg_u32 ssrc0, ssrc1 s_cmp_lg_u64 ssrc0, ssrc1 s_cmp_lt_f16 ssrc0, ssrc1 s_cmp_lt_f32 ssrc0, ssrc1 s_cmp_lt_i32 ssrc0, ssrc1 s_cmp_lt_u32 ssrc0, ssrc1 s_cmp_neq_f16 ssrc0, ssrc1 s_cmp_neq_f32 ssrc0, ssrc1 s_cmp_nge_f16 ssrc0, ssrc1 s_cmp_nge_f32 ssrc0, ssrc1 s_cmp_ngt_f16 ssrc0, ssrc1 s_cmp_ngt_f32 ssrc0, ssrc1 s_cmp_nle_f16 ssrc0, ssrc1 s_cmp_nle_f32 ssrc0, ssrc1 s_cmp_nlg_f16 ssrc0, ssrc1 s_cmp_nlg_f32 ssrc0, ssrc1 s_cmp_nlt_f16 ssrc0, ssrc1 s_cmp_nlt_f32 ssrc0, ssrc1 s_cmp_o_f16 ssrc0, ssrc1 s_cmp_o_f32 ssrc0, ssrc1 s_cmp_u_f16 ssrc0, ssrc1 s_cmp_u_f32 ssrc0, ssrc1
SOPK¶
INSTRUCTION DST SRC ——————————————————————————————————————————————————— s_addk_co_i32 sdst, simm16 s_call_b64 sdst, simm16 s_cmovk_i32 sdst, simm16 s_getreg_b32 sdst, simm16 s_movk_i32 sdst, simm16 s_mulk_i32 sdst, simm16 s_setreg_b32 simm16, sdst s_setreg_imm32_b32 simm16, literal s_version simm16
SOPP¶
INSTRUCTION SRC ————————————————————————————————————————— s_barrier_wait simm16 s_branch simm16 s_cbranch_execnz simm16 s_cbranch_execz simm16 s_cbranch_scc0 simm16 s_cbranch_scc1 simm16 s_cbranch_vccnz simm16 s_cbranch_vccz simm16 s_clause simm16 s_code_end s_decperflevel simm16 s_delay_alu simm16 s_denorm_mode simm16 s_endpgm s_endpgm_saved s_icache_inv s_incperflevel simm16 s_nop simm16 s_round_mode simm16 s_sendmsg simm16 s_sendmsghalt simm16 s_sethalt simm16 s_setkill simm16 s_setprio simm16 s_sleep simm16 s_trap simm16 s_ttracedata s_ttracedata_imm simm16 s_wait_alu simm16 s_wait_bvhcnt simm16 s_wait_dscnt simm16 s_wait_event simm16 s_wait_expcnt simm16 s_wait_idle s_wait_kmcnt simm16 s_wait_loadcnt simm16 s_wait_loadcnt_dscnt simm16 s_wait_samplecnt simm16 s_wait_storecnt simm16 s_wait_storecnt_dscnt simm16 s_wakeup
VBUFFER¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS ——————————————————————————————————————————————————————————————————————————————————————————————————————— buffer_atomic_add_f32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_add_u32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_add_u64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_and_b32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_and_b64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_cmpswap_b32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_cmpswap_b64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_cond_sub_u32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_dec_u32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_dec_u64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_inc_u32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_inc_u64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_max_i32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_max_i64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_max_num_f32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_max_u32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_max_u64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_min_i32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_min_i64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_min_num_f32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_min_u32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_min_u64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_or_b32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_or_b64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_pk_add_bf16 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_pk_add_f16 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_sub_clamp_u32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_sub_u32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_sub_u64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_swap_b32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_swap_b64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_xor_b32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_atomic_xor_b64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_b128 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_b32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_b64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_b96 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_b16 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_format_xy vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_format_xyz vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_format_xyzw vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_hi_b16 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_hi_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_hi_i8 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_hi_u8 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_i8 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_d16_u8 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_format_xy vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_format_xyz vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_format_xyzw vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_i16 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_i8 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_u16 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_load_u8 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_b128 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_b16 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_b32 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_b64 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_b8 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_b96 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_d16_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_d16_format_xy vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_d16_format_xyz vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_d16_format_xyzw vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_d16_hi_b16 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_d16_hi_b8 vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_d16_hi_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_format_xy vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_format_xyz vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv buffer_store_format_xyzw vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_load_d16_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_load_d16_format_xy vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_load_d16_format_xyz vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_load_d16_format_xyzw vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_load_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_load_format_xy vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_load_format_xyz vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_load_format_xyzw vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_store_d16_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_store_d16_format_xy vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_store_d16_format_xyz vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_store_d16_format_xyzw vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_store_format_x vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_store_format_xy vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_store_format_xyz vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv tbuffer_store_format_xyzw vdata, vaddr, rsrc, soffset offset idxen offen tfe th scope nv
VDS¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS ———————————————————————————————————————————————————————————————————————————————————————————————————— ds_add_f32 addr, data0 offset ds_add_rtn_f32 vdst, addr, data0 offset ds_add_rtn_u32 vdst, addr, data0 offset ds_add_rtn_u64 vdst, addr, data0 offset ds_add_u32 addr, data0 offset ds_add_u64 addr, data0 offset ds_and_b32 addr, data0 offset ds_and_b64 addr, data0 offset ds_and_rtn_b32 vdst, addr, data0 offset ds_and_rtn_b64 vdst, addr, data0 offset ds_append vdst offset ds_bpermute_b32 vdst, addr, data0 offset ds_bpermute_fi_b32 vdst, addr, data0 offset ds_bvh_stack_push4_pop1_rtn_b32 vdst, addr, data0, data1 offset ds_bvh_stack_push8_pop1_rtn_b32 vdst, addr, data0, data1 offset ds_bvh_stack_push8_pop2_rtn_b64 vdst, addr, data0, data1 offset ds_cmpstore_b32 addr, data0, data1 offset ds_cmpstore_b64 addr, data0, data1 offset ds_cmpstore_rtn_b32 vdst, addr, data0, data1 offset ds_cmpstore_rtn_b64 vdst, addr, data0, data1 offset ds_cond_sub_rtn_u32 vdst, addr, data0 offset ds_cond_sub_u32 addr, data0 offset ds_condxchg32_rtn_b64 vdst, addr, data0 offset ds_consume vdst offset ds_dec_rtn_u32 vdst, addr, data0 offset ds_dec_rtn_u64 vdst, addr, data0 offset ds_dec_u32 addr, data0 offset ds_dec_u64 addr, data0 offset ds_inc_rtn_u32 vdst, addr, data0 offset ds_inc_rtn_u64 vdst, addr, data0 offset ds_inc_u32 addr, data0 offset ds_inc_u64 addr, data0 offset ds_load_2addr_b32 vdst, addr offset0 offset1 ds_load_2addr_b64 vdst, addr offset0 offset1 ds_load_2addr_stride64_b32 vdst, addr offset0 offset1 ds_load_2addr_stride64_b64 vdst, addr offset0 offset1 ds_load_addtid_b32 vdst offset ds_load_b128 vdst, addr offset ds_load_b32 vdst, addr offset ds_load_b64 vdst, addr offset ds_load_b96 vdst, addr offset ds_load_i16 vdst, addr offset ds_load_i8 vdst, addr offset ds_load_i8_d16 vdst, addr offset ds_load_i8_d16_hi vdst, addr offset ds_load_u16 vdst, addr offset ds_load_u16_d16 vdst, addr offset ds_load_u16_d16_hi vdst, addr offset ds_load_u8 vdst, addr offset ds_load_u8_d16 vdst, addr offset ds_load_u8_d16_hi vdst, addr offset ds_max_i32 addr, data0 offset ds_max_i64 addr, data0 offset ds_max_num_f32 addr, data0 offset ds_max_num_f64 addr, data0 offset ds_max_num_rtn_f32 vdst, addr, data0 offset ds_max_num_rtn_f64 vdst, addr, data0 offset ds_max_rtn_i32 vdst, addr, data0 offset ds_max_rtn_i64 vdst, addr, data0 offset ds_max_rtn_u32 vdst, addr, data0 offset ds_max_rtn_u64 vdst, addr, data0 offset ds_max_u32 addr, data0 offset ds_max_u64 addr, data0 offset ds_min_i32 addr, data0 offset ds_min_i64 addr, data0 offset ds_min_num_f32 addr, data0 offset ds_min_num_f64 addr, data0 offset ds_min_num_rtn_f32 vdst, addr, data0 offset ds_min_num_rtn_f64 vdst, addr, data0 offset ds_min_rtn_i32 vdst, addr, data0 offset ds_min_rtn_i64 vdst, addr, data0 offset ds_min_rtn_u32 vdst, addr, data0 offset ds_min_rtn_u64 vdst, addr, data0 offset ds_min_u32 addr, data0 offset ds_min_u64 addr, data0 offset ds_mskor_b32 addr, data0, data1 offset ds_mskor_b64 addr, data0, data1 offset ds_mskor_rtn_b32 vdst, addr, data0, data1 offset ds_mskor_rtn_b64 vdst, addr, data0, data1 offset ds_nop offset ds_or_b32 addr, data0 offset ds_or_b64 addr, data0 offset ds_or_rtn_b32 vdst, addr, data0 offset ds_or_rtn_b64 vdst, addr, data0 offset ds_permute_b32 vdst, addr, data0 offset ds_pk_add_bf16 addr, data0 offset ds_pk_add_f16 addr, data0 offset ds_pk_add_rtn_bf16 vdst, addr, data0 offset ds_pk_add_rtn_f16 vdst, addr, data0 offset ds_rsub_rtn_u32 vdst, addr, data0 offset ds_rsub_rtn_u64 vdst, addr, data0 offset ds_rsub_u32 addr, data0 offset ds_rsub_u64 addr, data0 offset ds_store_2addr_b32 addr, data0, data1 offset0 offset1 ds_store_2addr_b64 addr, data0, data1 offset0 offset1 ds_store_2addr_stride64_b32 addr, data0, data1 offset0 offset1 ds_store_2addr_stride64_b64 addr, data0, data1 offset0 offset1 ds_store_addtid_b32 data0 offset ds_store_b128 addr, data0 offset ds_store_b16 addr, data0 offset ds_store_b16_d16_hi addr, data0 offset ds_store_b32 addr, data0 offset ds_store_b64 addr, data0 offset ds_store_b8 addr, data0 offset ds_store_b8_d16_hi addr, data0 offset ds_store_b96 addr, data0 offset ds_storexchg_2addr_rtn_b32 vdst, addr, data0, data1 offset0 offset1 ds_storexchg_2addr_rtn_b64 vdst, addr, data0, data1 offset0 offset1 ds_storexchg_2addr_stride64_rtn_b32 vdst, addr, data0, data1 offset0 offset1 ds_storexchg_2addr_stride64_rtn_b64 vdst, addr, data0, data1 offset0 offset1 ds_storexchg_rtn_b32 vdst, addr, data0 offset ds_storexchg_rtn_b64 vdst, addr, data0 offset ds_sub_clamp_rtn_u32 vdst, addr, data0 offset ds_sub_clamp_u32 addr, data0 offset ds_sub_rtn_u32 vdst, addr, data0 offset ds_sub_rtn_u64 vdst, addr, data0 offset ds_sub_u32 addr, data0 offset ds_sub_u64 addr, data0 offset ds_swizzle_b32 vdst, addr offset ds_xor_b32 addr, data0 offset ds_xor_b64 addr, data0 offset ds_xor_rtn_b32 vdst, addr, data0 offset ds_xor_rtn_b64 vdst, addr, data0 offset
VDSDIR¶
INSTRUCTION DST SRC MODIFIERS ——————————————————————————————————————————————————————————————————————————————————————————— ds_direct_load vdst wait_va_vdst wait_vdst wait_vm_vsrc ds_param_load vdst, attr wait_va_vdst wait_vdst wait_vm_vsrc
VEXPORT¶
INSTRUCTION DST SRC0 SRC1 SRC2 SRC3 MODIFIERS ————————————————————————————————————————————————————————————————————————————————————————————————— export tgt, vsrc0, vsrc1, vsrc2, vsrc3 done row_en
VFLAT¶
INSTRUCTION DST SRC0 SRC1 MODIFIERS ———————————————————————————————————————————————————————————————————————————————————— flat_atomic_add_f32 vdst, vaddr, vsrc offset th scope nv flat_atomic_add_u32 vdst, vaddr, vsrc offset th scope nv flat_atomic_add_u64 vdst, vaddr, vsrc offset th scope nv flat_atomic_and_b32 vdst, vaddr, vsrc offset th scope nv flat_atomic_and_b64 vdst, vaddr, vsrc offset th scope nv flat_atomic_cmpswap_b32 vdst, vaddr, vsrc offset th scope nv flat_atomic_cmpswap_b64 vdst, vaddr, vsrc offset th scope nv flat_atomic_cond_sub_u32 vdst, vaddr, vsrc offset th scope nv flat_atomic_dec_u32 vdst, vaddr, vsrc offset th scope nv flat_atomic_dec_u64 vdst, vaddr, vsrc offset th scope nv flat_atomic_inc_u32 vdst, vaddr, vsrc offset th scope nv flat_atomic_inc_u64 vdst, vaddr, vsrc offset th scope nv flat_atomic_max_i32 vdst, vaddr, vsrc offset th scope nv flat_atomic_max_i64 vdst, vaddr, vsrc offset th scope nv flat_atomic_max_num_f32 vdst, vaddr, vsrc offset th scope nv flat_atomic_max_u32 vdst, vaddr, vsrc offset th scope nv flat_atomic_max_u64 vdst, vaddr, vsrc offset th scope nv flat_atomic_min_i32 vdst, vaddr, vsrc offset th scope nv flat_atomic_min_i64 vdst, vaddr, vsrc offset th scope nv flat_atomic_min_num_f32 vdst, vaddr, vsrc offset th scope nv flat_atomic_min_u32 vdst, vaddr, vsrc offset th scope nv flat_atomic_min_u64 vdst, vaddr, vsrc offset th scope nv flat_atomic_or_b32 vdst, vaddr, vsrc offset th scope nv flat_atomic_or_b64 vdst, vaddr, vsrc offset th scope nv flat_atomic_pk_add_bf16 vdst, vaddr, vsrc offset th scope nv flat_atomic_pk_add_f16 vdst, vaddr, vsrc offset th scope nv flat_atomic_sub_clamp_u32 vdst, vaddr, vsrc offset th scope nv flat_atomic_sub_u32 vdst, vaddr, vsrc offset th scope nv flat_atomic_sub_u64 vdst, vaddr, vsrc offset th scope nv flat_atomic_swap_b32 vdst, vaddr, vsrc offset th scope nv flat_atomic_swap_b64 vdst, vaddr, vsrc offset th scope nv flat_atomic_xor_b32 vdst, vaddr, vsrc offset th scope nv flat_atomic_xor_b64 vdst, vaddr, vsrc offset th scope nv flat_load_b128 vdst, vaddr offset th scope nv flat_load_b32 vdst, vaddr offset th scope nv flat_load_b64 vdst, vaddr offset th scope nv flat_load_b96 vdst, vaddr offset th scope nv flat_load_d16_b16 vdst, vaddr offset th scope nv flat_load_d16_hi_b16 vdst, vaddr offset th scope nv flat_load_d16_hi_i8 vdst, vaddr offset th scope nv flat_load_d16_hi_u8 vdst, vaddr offset th scope nv flat_load_d16_i8 vdst, vaddr offset th scope nv flat_load_d16_u8 vdst, vaddr offset th scope nv flat_load_i16 vdst, vaddr offset th scope nv flat_load_i8 vdst, vaddr offset th scope nv flat_load_u16 vdst, vaddr offset th scope nv flat_load_u8 vdst, vaddr offset th scope nv flat_store_b128 vaddr, vsrc offset th scope nv flat_store_b16 vaddr, vsrc offset th scope nv flat_store_b32 vaddr, vsrc offset th scope nv flat_store_b64 vaddr, vsrc offset th scope nv flat_store_b8 vaddr, vsrc offset th scope nv flat_store_b96 vaddr, vsrc offset th scope nv flat_store_d16_hi_b16 vaddr, vsrc offset th scope nv flat_store_d16_hi_b8 vaddr, vsrc offset th scope nv
VGLOBAL¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS ————————————————————————————————————————————————————————————————————————————————————————————————— global_atomic_add_f32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_add_u32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_add_u64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_and_b32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_and_b64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_cmpswap_b32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_cmpswap_b64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_cond_sub_u32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_dec_u32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_dec_u64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_inc_u32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_inc_u64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_max_i32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_max_i64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_max_num_f32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_max_u32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_max_u64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_min_i32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_min_i64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_min_num_f32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_min_u32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_min_u64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_or_b32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_or_b64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_ordered_add_b64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_pk_add_bf16 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_pk_add_f16 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_sub_clamp_u32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_sub_u32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_sub_u64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_swap_b32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_swap_b64 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_xor_b32 vdst, vaddr, vsrc, saddr offset th scope nv global_atomic_xor_b64 vdst, vaddr, vsrc, saddr offset th scope nv global_inv offset th scope nv global_load_addtid_b32 vdst, saddr offset th scope nv global_load_b128 vdst, vaddr, saddr offset th scope nv global_load_b32 vdst, vaddr, saddr offset th scope nv global_load_b64 vdst, vaddr, saddr offset th scope nv global_load_b96 vdst, vaddr, saddr offset th scope nv global_load_block vdst, vaddr, saddr offset th scope nv global_load_d16_b16 vdst, vaddr, saddr offset th scope nv global_load_d16_hi_b16 vdst, vaddr, saddr offset th scope nv global_load_d16_hi_i8 vdst, vaddr, saddr offset th scope nv global_load_d16_hi_u8 vdst, vaddr, saddr offset th scope nv global_load_d16_i8 vdst, vaddr, saddr offset th scope nv global_load_d16_u8 vdst, vaddr, saddr offset th scope nv global_load_i16 vdst, vaddr, saddr offset th scope nv global_load_i8 vdst, vaddr, saddr offset th scope nv global_load_tr_b128 vdst, vaddr, saddr offset th scope nv global_load_tr_b64 vdst, vaddr, saddr offset th scope nv global_load_u16 vdst, vaddr, saddr offset th scope nv global_load_u8 vdst, vaddr, saddr offset th scope nv global_store_addtid_b32 vsrc, saddr offset th scope nv global_store_b128 vaddr, vsrc, saddr offset th scope nv global_store_b16 vaddr, vsrc, saddr offset th scope nv global_store_b32 vaddr, vsrc, saddr offset th scope nv global_store_b64 vaddr, vsrc, saddr offset th scope nv global_store_b8 vaddr, vsrc, saddr offset th scope nv global_store_b96 vaddr, vsrc, saddr offset th scope nv global_store_block vaddr, vsrc, saddr offset th scope nv global_store_d16_hi_b16 vaddr, vsrc, saddr offset th scope nv global_store_d16_hi_b8 vaddr, vsrc, saddr offset th scope nv global_wb offset th scope nv global_wbinv offset th scope nv
VIMAGE¶
INSTRUCTION DST SRC0 SRC1 MODIFIERS —————————————————————————————————————————————————————————————————————————————————————————————————————— image_atomic_add_flt vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_add_uint vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_and vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_cmpswap vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_dec_uint vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_inc_uint vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_max_flt vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_max_int vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_max_uint vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_min_flt vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_min_int vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_min_uint vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_or vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_pk_add_bf16 vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_pk_add_f16 vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_sub_uint vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_swap vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_atomic_xor vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_bvh64_intersect_ray vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_bvh8_intersect_ray vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_bvh_dual_intersect_ray vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_bvh_intersect_ray vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_get_resinfo vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_load vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_load_mip vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_load_mip_pck vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_load_mip_pck_sgn vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_load_pck vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_load_pck_sgn vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_store vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_store_mip vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_store_mip_pck vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv image_store_pck vdata, vaddr, rsrc dmask tfe dim r128 a16 d16 th scope nv
VINTERP¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS —————————————————————————————————————————————————————————————————————————————————————————— v_interp_p10_f16_f32 vdst, src0, src1, src2 clamp wait_exp v_interp_p10_f32 vdst, src0, src1, src2 clamp wait_exp v_interp_p10_rtz_f16_f32 vdst, src0, src1, src2 clamp wait_exp v_interp_p2_f16_f32 vdst, src0, src1, src2 clamp wait_exp v_interp_p2_f32 vdst, src0, src1, src2 clamp wait_exp v_interp_p2_rtz_f16_f32 vdst, src0, src1, src2 clamp wait_exp
VOP1¶
INSTRUCTION DST SRC ——————————————————————————————————————————————————— v_bfrev_b32 vdst, src0 v_ceil_f16 vdst, src0 v_ceil_f32 vdst, src0 v_ceil_f64 vdst, src0 v_cls_i32 vdst, src0 v_clz_i32_u32 vdst, src0 v_cos_f16 vdst, src0 v_cos_f32 vdst, src0 v_ctz_i32_b32 vdst, src0 v_cvt_f16_f32 vdst, src0 v_cvt_f16_i16 vdst, src0 v_cvt_f16_u16 vdst, src0 v_cvt_f32_bf8 vdst, src0 v_cvt_f32_f16 vdst, src0 v_cvt_f32_f64 vdst, src0 v_cvt_f32_fp8 vdst, src0 v_cvt_f32_i32 vdst, src0 v_cvt_f32_u32 vdst, src0 v_cvt_f32_ubyte0 vdst, src0 v_cvt_f32_ubyte1 vdst, src0 v_cvt_f32_ubyte2 vdst, src0 v_cvt_f32_ubyte3 vdst, src0 v_cvt_f64_f32 vdst, src0 v_cvt_f64_i32 vdst, src0 v_cvt_f64_u32 vdst, src0 v_cvt_floor_i32_f32 vdst, src0 v_cvt_i16_f16 vdst, src0 v_cvt_i32_f32 vdst, src0 v_cvt_i32_f64 vdst, src0 v_cvt_i32_i16 vdst, src0 v_cvt_nearest_i32_f32 vdst, src0 v_cvt_norm_i16_f16 vdst, src0 v_cvt_norm_u16_f16 vdst, src0 v_cvt_off_f32_i4 vdst, src0 v_cvt_pk_f32_bf8 vdst, src0 v_cvt_pk_f32_fp8 vdst, src0 v_cvt_u16_f16 vdst, src0 v_cvt_u32_f32 vdst, src0 v_cvt_u32_f64 vdst, src0 v_cvt_u32_u16 vdst, src0 v_exp_f16 vdst, src0 v_exp_f32 vdst, src0 v_floor_f16 vdst, src0 v_floor_f32 vdst, src0 v_floor_f64 vdst, src0 v_fract_f16 vdst, src0 v_fract_f32 vdst, src0 v_fract_f64 vdst, src0 v_frexp_exp_i16_f16 vdst, src0 v_frexp_exp_i32_f32 vdst, src0 v_frexp_exp_i32_f64 vdst, src0 v_frexp_mant_f16 vdst, src0 v_frexp_mant_f32 vdst, src0 v_frexp_mant_f64 vdst, src0 v_log_f16 vdst, src0 v_log_f32 vdst, src0 v_mov_b16 vdst, src0 v_mov_b32 vdst, src0 v_movreld_b32 vdst, src0 v_movrels_b32 vdst, src0 v_movrelsd_2_b32 vdst, src0 v_movrelsd_b32 vdst, src0 v_nop v_not_b16 vdst, src0 v_not_b32 vdst, src0 v_permlane64_b32 vdst, src0 v_pipeflush v_rcp_f16 vdst, src0 v_rcp_f32 vdst, src0 v_rcp_f64 vdst, src0 v_rcp_iflag_f32 vdst, src0 v_readfirstlane_b32 vdst, src0 v_rndne_f16 vdst, src0 v_rndne_f32 vdst, src0 v_rndne_f64 vdst, src0 v_rsq_f16 vdst, src0 v_rsq_f32 vdst, src0 v_rsq_f64 vdst, src0 v_sat_pk_u8_i16 vdst, src0 v_sin_f16 vdst, src0 v_sin_f32 vdst, src0 v_sqrt_f16 vdst, src0 v_sqrt_f32 vdst, src0 v_sqrt_f64 vdst, src0 v_swap_b16 vdst, src0 v_swap_b32 vdst, src0 v_swaprel_b32 vdst, src0 v_trunc_f16 vdst, src0 v_trunc_f32 vdst, src0 v_trunc_f64 vdst, src0
VOP2¶
INSTRUCTION DST0 DST1 SRC0 SRC1 SRC2 ————————————————————————————————————————————————————————————————————————————————— v_add_co_ci_u32 vdst, sdst, src0, vsrc1, vcc v_add_f16 vdst, src0, vsrc1 v_add_f32 vdst, src0, vsrc1 v_add_f64 vdst, src0, vsrc1 v_add_nc_u32 vdst, src0, vsrc1 v_and_b32 vdst, src0, vsrc1 v_ashrrev_i32 vdst, src0, vsrc1 v_cndmask_b32 vdst, src0, vsrc1, vcc v_cvt_pk_rtz_f16_f32 vdst, src0, vsrc1 v_fmaak_f16 vdst, src0, vsrc1, literal v_fmaak_f32 vdst, src0, vsrc1, literal v_fmac_f16 vdst, src0, vsrc1 v_fmac_f32 vdst, src0, vsrc1 v_fmamk_f16 vdst, src0, literal, vsrc1 v_fmamk_f32 vdst, src0, literal, vsrc1 v_ldexp_f16 vdst, src0, vsrc1 v_lshlrev_b32 vdst, src0, vsrc1 v_lshlrev_b64 vdst, src0, vsrc1 v_lshrrev_b32 vdst, src0, vsrc1 v_max_i32 vdst, src0, vsrc1 v_max_num_f16 vdst, src0, vsrc1 v_max_num_f32 vdst, src0, vsrc1 v_max_num_f64 vdst, src0, vsrc1 v_max_u32 vdst, src0, vsrc1 v_min_i32 vdst, src0, vsrc1 v_min_num_f16 vdst, src0, vsrc1 v_min_num_f32 vdst, src0, vsrc1 v_min_num_f64 vdst, src0, vsrc1 v_min_u32 vdst, src0, vsrc1 v_mul_dx9_zero_f32 vdst, src0, vsrc1 v_mul_f16 vdst, src0, vsrc1 v_mul_f32 vdst, src0, vsrc1 v_mul_f64 vdst, src0, vsrc1 v_mul_hi_i32_i24 vdst, src0, vsrc1 v_mul_hi_u32_u24 vdst, src0, vsrc1 v_mul_i32_i24 vdst, src0, vsrc1 v_mul_u32_u24 vdst, src0, vsrc1 v_or_b32 vdst, src0, vsrc1 v_pk_fmac_f16 vdst, src0, vsrc1 v_sub_co_ci_u32 vdst, sdst, src0, vsrc1, vcc v_sub_f16 vdst, src0, vsrc1 v_sub_f32 vdst, src0, vsrc1 v_sub_nc_u32 vdst, src0, vsrc1 v_subrev_co_ci_u32 vdst, sdst, src0, vsrc1, vcc v_subrev_f16 vdst, src0, vsrc1 v_subrev_f32 vdst, src0, vsrc1 v_subrev_nc_u32 vdst, src0, vsrc1 v_xnor_b32 vdst, src0, vsrc1 v_xor_b32 vdst, src0, vsrc1
VOP3¶
INSTRUCTION DST0 DST1 SRC0 SRC1 SRC2 ————————————————————————————————————————————————————————————————————————————————— v_add3_u32 vdst, src0, src1, src2 v_add_co_u32 vdst, sdst, src0, src1 v_add_lshl_u32 vdst, src0, src1, src2 v_add_nc_i16 vdst, src0, src1 v_add_nc_i32 vdst, src0, src1 v_add_nc_u16 vdst, src0, src1 v_alignbit_b32 vdst, src0, src1, src2 v_alignbyte_b32 vdst, src0, src1, src2 v_and_b16 vdst, src0, src1 v_and_or_b32 vdst, src0, src1, src2 v_ashrrev_i16 vdst, src0, src1 v_ashrrev_i64 vdst, src0, src1 v_bcnt_u32_b32 vdst, src0, src1 v_bfe_i32 vdst, src0, src1, src2 v_bfe_u32 vdst, src0, src1, src2 v_bfi_b32 vdst, src0, src1, src2 v_bfm_b32 vdst, src0, src1 v_cndmask_b16 vdst, src0, src1, src2 v_cubeid_f32 vdst, src0, src1, src2 v_cubema_f32 vdst, src0, src1, src2 v_cubesc_f32 vdst, src0, src1, src2 v_cubetc_f32 vdst, src0, src1, src2 v_cvt_pk_bf8_f32 vdst, src0, src1 v_cvt_pk_fp8_f32 vdst, src0, src1 v_cvt_pk_i16_f32 vdst, src0, src1 v_cvt_pk_i16_i32 vdst, src0, src1 v_cvt_pk_norm_i16_f16 vdst, src0, src1 v_cvt_pk_norm_i16_f32 vdst, src0, src1 v_cvt_pk_norm_u16_f16 vdst, src0, src1 v_cvt_pk_norm_u16_f32 vdst, src0, src1 v_cvt_pk_u16_f32 vdst, src0, src1 v_cvt_pk_u16_u32 vdst, src0, src1 v_cvt_pk_u8_f32 vdst, src0, src1, src2 v_cvt_sr_bf8_f32 vdst, src0, src1 v_cvt_sr_fp8_f32 vdst, src0, src1 v_div_fixup_f16 vdst, src0, src1, src2 v_div_fixup_f32 vdst, src0, src1, src2 v_div_fixup_f64 vdst, src0, src1, src2 v_div_fmas_f32 vdst, src0, src1, src2 v_div_fmas_f64 vdst, src0, src1, src2 v_div_scale_f32 vdst, sdst, src0, src1, src2 v_div_scale_f64 vdst, sdst, src0, src1, src2 v_dot2_bf16_bf16 vdst, src0, src1, src2 v_dot2_f16_f16 vdst, src0, src1, src2 v_fma_dx9_zero_f32 vdst, src0, src1, src2 v_fma_f16 vdst, src0, src1, src2 v_fma_f32 vdst, src0, src1, src2 v_fma_f64 vdst, src0, src1, src2 v_ldexp_f32 vdst, src0, src1 v_ldexp_f64 vdst, src0, src1 v_lerp_u8 vdst, src0, src1, src2 v_lshl_add_u32 vdst, src0, src1, src2 v_lshl_or_b32 vdst, src0, src1, src2 v_lshlrev_b16 vdst, src0, src1 v_lshrrev_b16 vdst, src0, src1 v_lshrrev_b64 vdst, src0, src1 v_mad_co_i64_i32 vdst, sdst, src0, src1, src2 v_mad_co_u64_u32 vdst, sdst, src0, src1, src2 v_mad_i16 vdst, src0, src1, src2 v_mad_i32_i16 vdst, src0, src1, src2 v_mad_i32_i24 vdst, src0, src1, src2 v_mad_u16 vdst, src0, src1, src2 v_mad_u32_u16 vdst, src0, src1, src2 v_mad_u32_u24 vdst, src0, src1, src2 v_max3_i16 vdst, src0, src1, src2 v_max3_i32 vdst, src0, src1, src2 v_max3_num_f16 vdst, src0, src1, src2 v_max3_num_f32 vdst, src0, src1, src2 v_max3_u16 vdst, src0, src1, src2 v_max3_u32 vdst, src0, src1, src2 v_max_i16 vdst, src0, src1 v_max_u16 vdst, src0, src1 v_maximum3_f16 vdst, src0, src1, src2 v_maximum3_f32 vdst, src0, src1, src2 v_maximum_f16 vdst, src0, src1 v_maximum_f32 vdst, src0, src1 v_maximum_f64 vdst, src0, src1 v_maximumminimum_f16 vdst, src0, src1, src2 v_maximumminimum_f32 vdst, src0, src1, src2 v_maxmin_i32 vdst, src0, src1, src2 v_maxmin_num_f16 vdst, src0, src1, src2 v_maxmin_num_f32 vdst, src0, src1, src2 v_maxmin_u32 vdst, src0, src1, src2 v_mbcnt_hi_u32_b32 vdst, src0, src1 v_mbcnt_lo_u32_b32 vdst, src0, src1 v_med3_i16 vdst, src0, src1, src2 v_med3_i32 vdst, src0, src1, src2 v_med3_num_f16 vdst, src0, src1, src2 v_med3_num_f32 vdst, src0, src1, src2 v_med3_u16 vdst, src0, src1, src2 v_med3_u32 vdst, src0, src1, src2 v_min3_i16 vdst, src0, src1, src2 v_min3_i32 vdst, src0, src1, src2 v_min3_num_f16 vdst, src0, src1, src2 v_min3_num_f32 vdst, src0, src1, src2 v_min3_u16 vdst, src0, src1, src2 v_min3_u32 vdst, src0, src1, src2 v_min_i16 vdst, src0, src1 v_min_u16 vdst, src0, src1 v_minimum3_f16 vdst, src0, src1, src2 v_minimum3_f32 vdst, src0, src1, src2 v_minimum_f16 vdst, src0, src1 v_minimum_f32 vdst, src0, src1 v_minimum_f64 vdst, src0, src1 v_minimummaximum_f16 vdst, src0, src1, src2 v_minimummaximum_f32 vdst, src0, src1, src2 v_minmax_i32 vdst, src0, src1, src2 v_minmax_num_f16 vdst, src0, src1, src2 v_minmax_num_f32 vdst, src0, src1, src2 v_minmax_u32 vdst, src0, src1, src2 v_mqsad_pk_u16_u8 vdst, src0, src1, src2 v_mqsad_u32_u8 vdst, src0, src1, src2 v_msad_u8 vdst, src0, src1, src2 v_mul_hi_i32 vdst, src0, src1 v_mul_hi_u32 vdst, src0, src1 v_mul_lo_u16 vdst, src0, src1 v_mul_lo_u32 vdst, src0, src1 v_mullit_f32 vdst, src0, src1, src2 v_or3_b32 vdst, src0, src1, src2 v_or_b16 vdst, src0, src1 v_pack_b32_f16 vdst, src0, src1 v_perm_b32 vdst, src0, src1, src2 v_permlane16_b32 vdst, src0, src1, src2 v_permlane16_var_b32 vdst, src0, src1 v_permlanex16_b32 vdst, src0, src1, src2 v_permlanex16_var_b32 vdst, src0, src1 v_qsad_pk_u16_u8 vdst, src0, src1, src2 v_readlane_b32 vdst, src0, src1 v_s_exp_f16 vdst, src0 v_s_exp_f32 vdst, src0 v_s_log_f16 vdst, src0 v_s_log_f32 vdst, src0 v_s_rcp_f16 vdst, src0 v_s_rcp_f32 vdst, src0 v_s_rsq_f16 vdst, src0 v_s_rsq_f32 vdst, src0 v_s_sqrt_f16 vdst, src0 v_s_sqrt_f32 vdst, src0 v_sad_hi_u8 vdst, src0, src1, src2 v_sad_u16 vdst, src0, src1, src2 v_sad_u32 vdst, src0, src1, src2 v_sad_u8 vdst, src0, src1, src2 v_sub_co_u32 vdst, sdst, src0, src1 v_sub_nc_i16 vdst, src0, src1 v_sub_nc_i32 vdst, src0, src1 v_sub_nc_u16 vdst, src0, src1 v_subrev_co_u32 vdst, sdst, src0, src1 v_trig_preop_f64 vdst, src0, src1 v_writelane_b32 vdst, src0, src1 v_xad_u32 vdst, src0, src1, src2 v_xor3_b32 vdst, src0, src1, src2 v_xor_b16 vdst, src0, src1
VOP3P¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS ———————————————————————————————————————————————————————————————————————————————————————— v_dot2_f32_bf16 vdst, src0, src1, src2 clamp v_dot2_f32_f16 vdst, src0, src1, src2 clamp v_dot4_f32_bf8_bf8 vdst, src0, src1, src2 clamp v_dot4_f32_bf8_fp8 vdst, src0, src1, src2 clamp v_dot4_f32_fp8_bf8 vdst, src0, src1, src2 clamp v_dot4_f32_fp8_fp8 vdst, src0, src1, src2 clamp v_dot4_i32_iu8 vdst, src0, src1, src2 clamp v_dot4_u32_u8 vdst, src0, src1, src2 clamp v_dot8_i32_iu4 vdst, src0, src1, src2 clamp v_dot8_u32_u4 vdst, src0, src1, src2 clamp v_fma_mix_f32 vdst, src0, src1, src2 clamp v_fma_mixhi_f16 vdst, src0, src1, src2 clamp v_fma_mixlo_f16 vdst, src0, src1, src2 clamp v_pk_add_f16 vdst, src0, src1 clamp v_pk_add_i16 vdst, src0, src1 clamp v_pk_add_u16 vdst, src0, src1 clamp v_pk_ashrrev_i16 vdst, src0, src1 clamp v_pk_fma_f16 vdst, src0, src1, src2 clamp v_pk_lshlrev_b16 vdst, src0, src1 clamp v_pk_lshrrev_b16 vdst, src0, src1 clamp v_pk_mad_i16 vdst, src0, src1, src2 clamp v_pk_mad_u16 vdst, src0, src1, src2 clamp v_pk_max_i16 vdst, src0, src1 clamp v_pk_max_num_f16 vdst, src0, src1 clamp v_pk_max_u16 vdst, src0, src1 clamp v_pk_maximum_f16 vdst, src0, src1 clamp v_pk_min_i16 vdst, src0, src1 clamp v_pk_min_num_f16 vdst, src0, src1 clamp v_pk_min_u16 vdst, src0, src1 clamp v_pk_minimum_f16 vdst, src0, src1 clamp v_pk_mul_f16 vdst, src0, src1 clamp v_pk_mul_lo_u16 vdst, src0, src1 clamp v_pk_sub_i16 vdst, src0, src1 clamp v_pk_sub_u16 vdst, src0, src1 clamp v_swmmac_bf16_16x16x32_bf16 vdst, src0, src1, src2 clamp v_swmmac_f16_16x16x32_f16 vdst, src0, src1, src2 clamp v_swmmac_f32_16x16x32_bf16 vdst, src0, src1, src2 clamp v_swmmac_f32_16x16x32_bf8_bf8 vdst, src0, src1, src2 clamp v_swmmac_f32_16x16x32_bf8_fp8 vdst, src0, src1, src2 clamp v_swmmac_f32_16x16x32_f16 vdst, src0, src1, src2 clamp v_swmmac_f32_16x16x32_fp8_bf8 vdst, src0, src1, src2 clamp v_swmmac_f32_16x16x32_fp8_fp8 vdst, src0, src1, src2 clamp v_swmmac_i32_16x16x32_iu4 vdst, src0, src1, src2 clamp v_swmmac_i32_16x16x32_iu8 vdst, src0, src1, src2 clamp v_swmmac_i32_16x16x64_iu4 vdst, src0, src1, src2 clamp v_wmma_bf16_16x16x16_bf16 vdst, src0, src1, src2 clamp v_wmma_f16_16x16x16_f16 vdst, src0, src1, src2 clamp v_wmma_f32_16x16x16_bf16 vdst, src0, src1, src2 clamp v_wmma_f32_16x16x16_bf8_bf8 vdst, src0, src1, src2 clamp v_wmma_f32_16x16x16_bf8_fp8 vdst, src0, src1, src2 clamp v_wmma_f32_16x16x16_f16 vdst, src0, src1, src2 clamp v_wmma_f32_16x16x16_fp8_bf8 vdst, src0, src1, src2 clamp v_wmma_f32_16x16x16_fp8_fp8 vdst, src0, src1, src2 clamp v_wmma_i32_16x16x16_iu4 vdst, src0, src1, src2 clamp v_wmma_i32_16x16x16_iu8 vdst, src0, src1, src2 clamp v_wmma_i32_16x16x32_iu4 vdst, src0, src1, src2 clamp
VOPC¶
INSTRUCTION DST SRC0 SRC1 ————————————————————————————————————————————————————————————— v_cmp_class_f16 vdst, src0, vsrc1 v_cmp_class_f32 vdst, src0, vsrc1 v_cmp_class_f64 vdst, src0, vsrc1 v_cmp_eq_f16 vdst, src0, vsrc1 v_cmp_eq_f32 vdst, src0, vsrc1 v_cmp_eq_f64 vdst, src0, vsrc1 v_cmp_eq_i16 vdst, src0, vsrc1 v_cmp_eq_i32 vdst, src0, vsrc1 v_cmp_eq_i64 vdst, src0, vsrc1 v_cmp_eq_u16 vdst, src0, vsrc1 v_cmp_eq_u32 vdst, src0, vsrc1 v_cmp_eq_u64 vdst, src0, vsrc1 v_cmp_ge_f16 vdst, src0, vsrc1 v_cmp_ge_f32 vdst, src0, vsrc1 v_cmp_ge_f64 vdst, src0, vsrc1 v_cmp_ge_i16 vdst, src0, vsrc1 v_cmp_ge_i32 vdst, src0, vsrc1 v_cmp_ge_i64 vdst, src0, vsrc1 v_cmp_ge_u16 vdst, src0, vsrc1 v_cmp_ge_u32 vdst, src0, vsrc1 v_cmp_ge_u64 vdst, src0, vsrc1 v_cmp_gt_f16 vdst, src0, vsrc1 v_cmp_gt_f32 vdst, src0, vsrc1 v_cmp_gt_f64 vdst, src0, vsrc1 v_cmp_gt_i16 vdst, src0, vsrc1 v_cmp_gt_i32 vdst, src0, vsrc1 v_cmp_gt_i64 vdst, src0, vsrc1 v_cmp_gt_u16 vdst, src0, vsrc1 v_cmp_gt_u32 vdst, src0, vsrc1 v_cmp_gt_u64 vdst, src0, vsrc1 v_cmp_le_f16 vdst, src0, vsrc1 v_cmp_le_f32 vdst, src0, vsrc1 v_cmp_le_f64 vdst, src0, vsrc1 v_cmp_le_i16 vdst, src0, vsrc1 v_cmp_le_i32 vdst, src0, vsrc1 v_cmp_le_i64 vdst, src0, vsrc1 v_cmp_le_u16 vdst, src0, vsrc1 v_cmp_le_u32 vdst, src0, vsrc1 v_cmp_le_u64 vdst, src0, vsrc1 v_cmp_lg_f16 vdst, src0, vsrc1 v_cmp_lg_f32 vdst, src0, vsrc1 v_cmp_lg_f64 vdst, src0, vsrc1 v_cmp_lt_f16 vdst, src0, vsrc1 v_cmp_lt_f32 vdst, src0, vsrc1 v_cmp_lt_f64 vdst, src0, vsrc1 v_cmp_lt_i16 vdst, src0, vsrc1 v_cmp_lt_i32 vdst, src0, vsrc1 v_cmp_lt_i64 vdst, src0, vsrc1 v_cmp_lt_u16 vdst, src0, vsrc1 v_cmp_lt_u32 vdst, src0, vsrc1 v_cmp_lt_u64 vdst, src0, vsrc1 v_cmp_ne_i16 vdst, src0, vsrc1 v_cmp_ne_i32 vdst, src0, vsrc1 v_cmp_ne_i64 vdst, src0, vsrc1 v_cmp_ne_u16 vdst, src0, vsrc1 v_cmp_ne_u32 vdst, src0, vsrc1 v_cmp_ne_u64 vdst, src0, vsrc1 v_cmp_neq_f16 vdst, src0, vsrc1 v_cmp_neq_f32 vdst, src0, vsrc1 v_cmp_neq_f64 vdst, src0, vsrc1 v_cmp_nge_f16 vdst, src0, vsrc1 v_cmp_nge_f32 vdst, src0, vsrc1 v_cmp_nge_f64 vdst, src0, vsrc1 v_cmp_ngt_f16 vdst, src0, vsrc1 v_cmp_ngt_f32 vdst, src0, vsrc1 v_cmp_ngt_f64 vdst, src0, vsrc1 v_cmp_nle_f16 vdst, src0, vsrc1 v_cmp_nle_f32 vdst, src0, vsrc1 v_cmp_nle_f64 vdst, src0, vsrc1 v_cmp_nlg_f16 vdst, src0, vsrc1 v_cmp_nlg_f32 vdst, src0, vsrc1 v_cmp_nlg_f64 vdst, src0, vsrc1 v_cmp_nlt_f16 vdst, src0, vsrc1 v_cmp_nlt_f32 vdst, src0, vsrc1 v_cmp_nlt_f64 vdst, src0, vsrc1 v_cmp_o_f16 vdst, src0, vsrc1 v_cmp_o_f32 vdst, src0, vsrc1 v_cmp_o_f64 vdst, src0, vsrc1 v_cmp_u_f16 vdst, src0, vsrc1 v_cmp_u_f32 vdst, src0, vsrc1 v_cmp_u_f64 vdst, src0, vsrc1 v_cmpx_class_f16 vdst, src0, vsrc1 v_cmpx_class_f32 vdst, src0, vsrc1 v_cmpx_class_f64 vdst, src0, vsrc1 v_cmpx_eq_f16 vdst, src0, vsrc1 v_cmpx_eq_f32 vdst, src0, vsrc1 v_cmpx_eq_f64 vdst, src0, vsrc1 v_cmpx_eq_i16 vdst, src0, vsrc1 v_cmpx_eq_i32 vdst, src0, vsrc1 v_cmpx_eq_i64 vdst, src0, vsrc1 v_cmpx_eq_u16 vdst, src0, vsrc1 v_cmpx_eq_u32 vdst, src0, vsrc1 v_cmpx_eq_u64 vdst, src0, vsrc1 v_cmpx_ge_f16 vdst, src0, vsrc1 v_cmpx_ge_f32 vdst, src0, vsrc1 v_cmpx_ge_f64 vdst, src0, vsrc1 v_cmpx_ge_i16 vdst, src0, vsrc1 v_cmpx_ge_i32 vdst, src0, vsrc1 v_cmpx_ge_i64 vdst, src0, vsrc1 v_cmpx_ge_u16 vdst, src0, vsrc1 v_cmpx_ge_u32 vdst, src0, vsrc1 v_cmpx_ge_u64 vdst, src0, vsrc1 v_cmpx_gt_f16 vdst, src0, vsrc1 v_cmpx_gt_f32 vdst, src0, vsrc1 v_cmpx_gt_f64 vdst, src0, vsrc1 v_cmpx_gt_i16 vdst, src0, vsrc1 v_cmpx_gt_i32 vdst, src0, vsrc1 v_cmpx_gt_i64 vdst, src0, vsrc1 v_cmpx_gt_u16 vdst, src0, vsrc1 v_cmpx_gt_u32 vdst, src0, vsrc1 v_cmpx_gt_u64 vdst, src0, vsrc1 v_cmpx_le_f16 vdst, src0, vsrc1 v_cmpx_le_f32 vdst, src0, vsrc1 v_cmpx_le_f64 vdst, src0, vsrc1 v_cmpx_le_i16 vdst, src0, vsrc1 v_cmpx_le_i32 vdst, src0, vsrc1 v_cmpx_le_i64 vdst, src0, vsrc1 v_cmpx_le_u16 vdst, src0, vsrc1 v_cmpx_le_u32 vdst, src0, vsrc1 v_cmpx_le_u64 vdst, src0, vsrc1 v_cmpx_lg_f16 vdst, src0, vsrc1 v_cmpx_lg_f32 vdst, src0, vsrc1 v_cmpx_lg_f64 vdst, src0, vsrc1 v_cmpx_lt_f16 vdst, src0, vsrc1 v_cmpx_lt_f32 vdst, src0, vsrc1 v_cmpx_lt_f64 vdst, src0, vsrc1 v_cmpx_lt_i16 vdst, src0, vsrc1 v_cmpx_lt_i32 vdst, src0, vsrc1 v_cmpx_lt_i64 vdst, src0, vsrc1 v_cmpx_lt_u16 vdst, src0, vsrc1 v_cmpx_lt_u32 vdst, src0, vsrc1 v_cmpx_lt_u64 vdst, src0, vsrc1 v_cmpx_ne_i16 vdst, src0, vsrc1 v_cmpx_ne_i32 vdst, src0, vsrc1 v_cmpx_ne_i64 vdst, src0, vsrc1 v_cmpx_ne_u16 vdst, src0, vsrc1 v_cmpx_ne_u32 vdst, src0, vsrc1 v_cmpx_ne_u64 vdst, src0, vsrc1 v_cmpx_neq_f16 vdst, src0, vsrc1 v_cmpx_neq_f32 vdst, src0, vsrc1 v_cmpx_neq_f64 vdst, src0, vsrc1 v_cmpx_nge_f16 vdst, src0, vsrc1 v_cmpx_nge_f32 vdst, src0, vsrc1 v_cmpx_nge_f64 vdst, src0, vsrc1 v_cmpx_ngt_f16 vdst, src0, vsrc1 v_cmpx_ngt_f32 vdst, src0, vsrc1 v_cmpx_ngt_f64 vdst, src0, vsrc1 v_cmpx_nle_f16 vdst, src0, vsrc1 v_cmpx_nle_f32 vdst, src0, vsrc1 v_cmpx_nle_f64 vdst, src0, vsrc1 v_cmpx_nlg_f16 vdst, src0, vsrc1 v_cmpx_nlg_f32 vdst, src0, vsrc1 v_cmpx_nlg_f64 vdst, src0, vsrc1 v_cmpx_nlt_f16 vdst, src0, vsrc1 v_cmpx_nlt_f32 vdst, src0, vsrc1 v_cmpx_nlt_f64 vdst, src0, vsrc1 v_cmpx_o_f16 vdst, src0, vsrc1 v_cmpx_o_f32 vdst, src0, vsrc1 v_cmpx_o_f64 vdst, src0, vsrc1 v_cmpx_u_f16 vdst, src0, vsrc1 v_cmpx_u_f32 vdst, src0, vsrc1 v_cmpx_u_f64 vdst, src0, vsrc1
VOPDX¶
INSTRUCTION DST SRC0 SRC1 SRC2 ——————————————————————————————————————————————————————————————————————— v_dual_add_f32 vdstx, srcx0, vsrcx1 v_dual_cndmask_b32 vdstx, srcx0, vsrcx1, vcc v_dual_dot2acc_f32_bf16 vdstx, srcx0, vsrcx1 v_dual_dot2acc_f32_f16 vdstx, srcx0, vsrcx1 v_dual_fmaak_f32 vdstx, srcx0, vsrcx1, literal v_dual_fmac_f32 vdstx, srcx0, vsrcx1 v_dual_fmamk_f32 vdstx, srcx0, literal, vsrcx1 v_dual_max_num_f32 vdstx, srcx0, vsrcx1 v_dual_min_num_f32 vdstx, srcx0, vsrcx1 v_dual_mov_b32 vdstx, srcx0 v_dual_mul_dx9_zero_f32 vdstx, srcx0, vsrcx1 v_dual_mul_f32 vdstx, srcx0, vsrcx1 v_dual_sub_f32 vdstx, srcx0, vsrcx1 v_dual_subrev_f32 vdstx, srcx0, vsrcx1
VOPDY¶
INSTRUCTION DST SRC0 SRC1 ————————————————————————————————————————————————————————————— v_dual_add_nc_u32 vdsty, srcy0, vsrcy1 v_dual_and_b32 vdsty, srcy0, vsrcy1 v_dual_lshlrev_b32 vdsty, srcy0, vsrcy1
VSAMPLE¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS ————————————————————————————————————————————————————————————————————————————————————————————————————— image_gather4 vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_b vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_b_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_c vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_c_b vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_c_b_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_c_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_c_l vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_c_lz vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_c_lz_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_l vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_lz vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_lz_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_gather4h vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_get_lod vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_msaa_load vdata, vaddr, rsrc dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_b vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_b_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_b_cl_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_b_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_b vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_b_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_b_cl_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_b_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_cl_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_d vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_d_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_d_cl_g16 vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_d_cl_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_d_cl_o_g16 vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_d_g16 vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_d_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_d_o_g16 vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_l vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_l_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_lz vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_lz_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_c_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_cl_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_d vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_d_cl vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_d_cl_g16 vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_d_cl_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_d_cl_o_g16 vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_d_g16 vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_d_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_d_o_g16 vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_l vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_l_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_lz vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_lz_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv image_sample_o vdata, vaddr, rsrc, samp dmask tfe unorm lwe dim r128 a16 d16 th scope nv
VSCRATCH¶
INSTRUCTION DST SRC0 SRC1 SRC2 MODIFIERS —————————————————————————————————————————————————————————————————————————————————————————————— scratch_load_b128 vdst, vaddr, saddr offset th scope nv scratch_load_b32 vdst, vaddr, saddr offset th scope nv scratch_load_b64 vdst, vaddr, saddr offset th scope nv scratch_load_b96 vdst, vaddr, saddr offset th scope nv scratch_load_block vdst, vaddr, saddr offset th scope nv scratch_load_d16_b16 vdst, vaddr, saddr offset th scope nv scratch_load_d16_hi_b16 vdst, vaddr, saddr offset th scope nv scratch_load_d16_hi_i8 vdst, vaddr, saddr offset th scope nv scratch_load_d16_hi_u8 vdst, vaddr, saddr offset th scope nv scratch_load_d16_i8 vdst, vaddr, saddr offset th scope nv scratch_load_d16_u8 vdst, vaddr, saddr offset th scope nv scratch_load_i16 vdst, vaddr, saddr offset th scope nv scratch_load_i8 vdst, vaddr, saddr offset th scope nv scratch_load_u16 vdst, vaddr, saddr offset th scope nv scratch_load_u8 vdst, vaddr, saddr offset th scope nv scratch_store_b128 vaddr, vsrc, saddr offset th scope nv scratch_store_b16 vaddr, vsrc, saddr offset th scope nv scratch_store_b32 vaddr, vsrc, saddr offset th scope nv scratch_store_b64 vaddr, vsrc, saddr offset th scope nv scratch_store_b8 vaddr, vsrc, saddr offset th scope nv scratch_store_b96 vaddr, vsrc, saddr offset th scope nv scratch_store_block vaddr, vsrc, saddr offset th scope nv scratch_store_d16_hi_b16 vaddr, vsrc, saddr offset th scope nv scratch_store_d16_hi_b8 vaddr, vsrc, saddr offset th scope nv